SVC

SuperVisor Call.

Show/hideSyntax

SVC{cond} #imm

where:

cond

is an optional condition code.

imm

is an expression evaluating to an integer in the range:

  • 0 to 224-1 (a 24-bit value) in an ARM instruction

  • 0-255 (an 8-bit value) in a 16-bit Thumb instruction.

Show/hideUsage

The SVC instruction causes an exception. This means that the processor mode changes to Supervisor, the CPSR is saved to the Supervisor mode SPSR, and execution branches to the SVC vector.

imm is ignored by the processor. However, it can be retrieved by the exception handler to determine what service is being requested.

Note

SVC was called SWI in earlier versions of the ARM assembly language. SWI instructions disassemble to SVC, with a comment to say that this was formerly SWI.

Show/hideCondition flags

This instruction does not change the flags.

Show/hideArchitectures

This ARM instruction is available in all versions of the ARM architecture.

This 16-bit Thumb instruction is available in all T variants of the ARM architecture.

There is no 32-bit Thumb version of this instruction.

Show/hideSee also

Concepts

Developing Software for ARM Processors:

Reference
Copyright © 2010-2011 ARM. All rights reserved.ARM DUI 0489F
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