QADD, QSUB, QDADD, and QDSUB

Signed Add, Subtract, Double and Add, Double and Subtract, saturating the result to the signed range -231x ≤ 231-1.

Show/hideSyntax

op{cond} {Rd}, Rm, Rn

where:

op

is one of QADD, QSUB, QDADD, or QDSUB.

cond

is an optional condition code.

Rd

is the destination register.

Rm, Rn

are the registers holding the operands.

Show/hideUsage

The QADD instruction adds the values in Rm and Rn.

The QSUB instruction subtracts the value in Rn from the value in Rm.

The QDADD instruction calculates SAT(Rm + SAT(Rn * 2)). Saturation can occur on the doubling operation, on the addition, or on both. If saturation occurs on the doubling but not on the addition, the Q flag is set but the final result is unsaturated.

The QDSUB instruction calculates SAT(Rm - SAT(Rn * 2)). Saturation can occur on the doubling operation, on the subtraction, or on both. If saturation occurs on the doubling but not on the subtraction, the Q flag is set but the final result is unsaturated.

Note

All values are treated as two’s complement signed integers by these instructions.

Show/hideRegister restrictions

You cannot use PC for any operand.

You can use SP in ARM instructions but these are deprecated in ARMv6T2 and above. You cannot use SP in Thumb instructions.

Show/hideCondition flags

If saturation occurs, these instructions set the Q flag. To read the state of the Q flag, use an MRS instruction.

Show/hideArchitectures

These ARM instructions are available in ARMv6 and above, and E variants of ARMv5T.

These 32-bit Thumb instructions are available in ARMv6T2 and above. For the ARMv7-M architecture, they are only available in an ARMv7E-M implementation.

There are no 16-bit Thumb versions of these instructions.

Show/hideExamples

    QADD    r0, r1, r9
    QDSUBLT r9, r0, r1

Show/hideSee also

Copyright © 2010-2011 ARM. All rights reserved.ARM DUI 0489F
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