ADR (PC-relative)

ADR generates a PC-relative address in the destination register, for a label in the current area.


ADR{cond}{.W} Rd,label



is an optional condition code.


is an optional instruction width specifier.


is the destination register to load.


is a PC-relative expression.

label must be within a limited distance of the current instruction.


ADR produces position-independent code, because the assembler generates an instruction that adds or subtracts a value to the PC.

Use the ADRL pseudo-instruction to assemble a wider range of effective addresses.

label must evaluate to an address in the same assembler area as the ADR instruction.

If you use ADR to generate a target for a BX or BLX instruction, it is your responsibility to set the Thumb bit (bit 0) of the address if the target contains Thumb instructions.

Show/hideOffset range and architectures

The assembler calculates the offset from the PC for you. The assembler generates an error if label is out of range.

Table 8 shows the possible offsets between label and the current instruction.

Table 10. PC-relative offsets

InstructionOffset rangeArchitectures
ARM ADRSee Operand2 as a constantAll
32-bit Thumb ADR+/- 4095v6T2, v7
16-bit Thumb ADR [a]0-1020 [b]All T

[a] Rd must be in the range R0-R7.

[b] Must be a multiple of 4.

Show/hideADR in 32-bit Thumb

You can use the .W width specifier to force ADR to generate a 32-bit instruction in Thumb code. ADR with .W always generates a 32-bit instruction, even if the address can be generated in a 16-bit instruction.

For forward references, ADR without .W always generates a 16-bit instruction in Thumb code, even if that results in failure for an address that could be generated in a 32-bit Thumb ADD instruction.


In Thumb code, Rd cannot be PC or SP.

In ARM code, Rd can be PC or SP but use of SP is deprecated in ARMv6T2 and above.

Show/hideSee also

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