Transfer Data between memory and Coprocessor.
Syntaxop{L}{cond}coproc,CRd, [Rn]
op{L}{cond}coproc,CRd, [Rn, #{-}offset] ; offset addressing
op{L}{cond}coproc,CRd, [Rn, #{-}offset]! ; pre-index addressing
op{L}{cond}coproc, CRd, [Rn],#{-}offset; post-index addressing
op{L}{cond}coproc,CRd,label
where:
opis one of
LDC,LDC2,STC, orSTC2.condis an optional condition code.
In ARM code,
condLDC2orSTC2.Lis an optional suffix specifying a long transfer.
coprocis the name of the coprocessor the instruction is for. The standard name is
p, wherennCRdis the coprocessor register to load or store.
Rnis the register on which the memory address is based. If PC is specified, the value used is the address of the current instruction plus eight.
-is an optional minus sign. If
-is present, the offset is subtracted fromRnRnoffsetis an expression evaluating to a multiple of 4, in the range 0 to 1020.
!is an optional suffix. If ! is present, the address including the offset is written back into
Rnlabelis a word-aligned PC-relative expression.
label
The use of these instructions depends on the coprocessor. See the coprocessor documentation for details.
In ThumbEE, if the value in the base register is zero, execution branches to the NullCheck handler at HandlerBase - 4.
LDC and STC are available in all
versions of the ARM architecture.
LDC2 and STC2 are available in ARMv5T
and above.
These 32-bit Thumb instructions are available in ARMv6T2 and above.
There are no 16-bit Thumb versions of these instructions.
You cannot use PC for R in
the pre-index and post-index instructions. These are the forms that write
back to nR.n
You cannot use PC for R in
Thumb nSTC and STC2 instructions.
ARM STC and STC2 instructions that
use the label syntax, or where R is
PC, are deprecated in ARMv6T2 and above.n
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