Various byte-wise and halfword-wise additions and subtractions.
Syntax<prefix>op{cond} {Rd},Rn,Rm
where:
<prefix>is one of:
SSigned arithmetic modulo 28 or 216. Sets APSR GE flags.
QSigned saturating arithmetic.
SHSigned arithmetic, halving the results.
UUnsigned arithmetic modulo 28 or 216. Sets APSR GE flags.
UQUnsigned saturating arithmetic.
UHUnsigned arithmetic, halving the results.
opis one of:
ADD8Byte-wise Addition
ADD16Halfword-wise Addition.
SUB8Byte-wise Subtraction.
SUB16Halfword-wise Subtraction.
ASXExchange halfwords of
RmSAXExchange halfwords of
Rm
condis an optional condition code.
Rdis the destination register.
Rm, Rnare the ARM registers holding the operands.
These instructions perform arithmetic operations separately on the bytes or halfwords of the operands. They perform two or four additions or subtractions, or one addition and one subtraction.
You can choose various kinds of arithmetic:
Signed or unsigned arithmetic modulo 28 or 216. This sets the APSR GE flags.
Signed saturating arithmetic to one of the signed ranges -215 ≤
x≤ 215 -1 or -27 ≤x≤ 27 -1. The Q flag is not affected even if these operations saturate.Unsigned saturating arithmetic to one of the unsigned ranges 0 ≤
x≤ 216 -1 or 0 ≤x≤ 28 -1. The Q flag is not affected even if these operations saturate.Signed or unsigned arithmetic, halving the results. This cannot cause overflow.
You cannot use PC for any register.
You can use SP in ARM instructions but these are deprecated in ARMv6T2 and above. You cannot use SP in Thumb instructions.
These instructions do not affect the N, Z, C, V, or Q flags.
The Q, SH, UQ and UH prefix
variants of these instructions do not change the flags.
The S and U prefix variants
of these instructions set the GE flags in the APSR as follows:
For byte-wise operations, the GE flags are used in the same way as the C (Carry) flag for 32-bit
SUBandADDinstructions:GE[0]for bits[7:0] of the result
GE[1]for bits[15:8] of the result
GE[2]for bits[23:16] of the result
GE[3]for bits[31:24] of the result.
For halfword-wise operations, the GE flags are used in the same way as the C (Carry) flag for normal word-wise
SUBandADDinstructions:GE[1:0]for bits[15:0] of the result
GE[3:2]for bits[31:16] of the result.
You can use these flags to control a following SEL instruction.
Note
For halfword-wise operations, GE[1:0] are set or cleared together, and GE[3:2] are set or cleared together.
These ARM instructions are available in ARMv6 and above.
These 32-bit Thumb instructions are available in ARMv6T2 and above. For the ARMv7-M architecture, they are only available in an ARMv7E-M implementation.
There are no 16-bit Thumb versions of these instructions.
QHADD r2, r9, r3 ; No such instruction, should be QHADD8 or QHADD16
SAX r10, r8, r5 ; Must have a prefix.
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