ASR, LSL, LSR, ROR, and RRX

Arithmetic Shift Right, Logical Shift Left, Logical Shift Right, Rotate Right, and Rotate Right with Extend.

These instructions are the preferred synonyms for MOV instructions with shifted register operands.

Show/hideSyntax

op{S}{cond} Rd, Rm, Rs
op{S}{cond} Rd, Rm, #sh
RRX{S}{cond} Rd, Rm

where:

op

is one of ASR, LSL, LSR, or ROR.

S

is an optional suffix. If S is specified, the condition code flags are updated on the result of the operation.

Rd

is the destination register.

Rm

is the register holding the first operand. This operand is shifted right.

Rs

is a register holding a shift value to apply to the value in Rm. Only the least significant byte is used.

sh

is a constant shift. The range of values permitted depends on the instruction:

ASR

permitted shifts 1-32

LSL

permitted shifts 0-31

LSR

permitted shifts 1-32

ROR

permitted shifts 1-31.

Show/hideUsage

ASR provides the signed value of the contents of a register divided by a power of two. It copies the sign bit into vacated bit positions on the left.

LSL provides the value of a register multiplied by a power of two. LSR provides the unsigned value of a register divided by a variable power of two. Both instructions insert zeros into the vacated bit positions.

ROR provides the value of the contents of a register rotated by a value. The bits that are rotated off the right end are inserted into the vacated bit positions on the left.

RRX provides the value of the contents of a register shifted right one bit. The old carry flag is shifted into bit[31]. If the S suffix is present, the old bit[0] is placed in the carry flag.

Show/hideRestrictions in Thumb code

Thumb instructions must not use PC or SP.

If you specify zero for the sh value in an LSL instruction in an IT block, the result is unpredictable.

Show/hideUse of SP and PC in ARM ASR, LSL, LSR, ROR, and RRX instructions

You can use SP in these ARM instructions but these are deprecated in ARMv6T2 and above.

You cannot use PC in instructions with the op{S}{cond} Rd, Rm, Rs syntax. You can use PC for Rd and Rm in the other syntaxes, but these are deprecated in ARMv6T2 and above.

If you use PC as Rm, the value used is the address of the instruction plus 8.

If you use PC as Rd:

  • Execution branches to the address corresponding to the result.

  • If you use the S suffix, the SPSR of the current mode is copied to the CPSR. You can use this to return from exceptions.

    Note

    The ARM instructions opS{cond} pc,Rm,#sh and RRXS{cond} pc,Rm always disassemble to the preferred form MOVS{cond} pc,Rm{,shift}.

Caution

Do not use the S suffix when using PC as Rd in User mode or System mode. The effect of such an instruction is unpredictable, but the assembler cannot warn you at assembly time.

You cannot use PC for Rd or any operand in any of these instructions if they have a register-controlled shift.

Show/hideCondition flags

If S is specified, these instructions update the N and Z flags according to the result.

The C flag is unaffected if the shift value is 0. Otherwise, the C flag is updated to the last bit shifted out.

Show/hide16-bit instructions

The following forms of these instructions are available in Thumb code, and are 16-bit instructions:

ASRS Rd, Rm, #sh

Rd and Rm must both be Lo registers.

ASRS Rd, Rd, Rs

Rd and Rs must both be Lo registers.

LSLS Rd, Rm, #sh

Rd and Rm must both be Lo registers.

LSLS Rd, Rd, Rs

Rd and Rs must both be Lo registers.

LSRS Rd, Rm, #sh

Rd and Rm must both be Lo registers.

LSRS Rd, Rd, Rs

Rd and Rs must both be Lo registers.

RORS Rd, Rd, Rs

Rd and Rs must both be Lo registers.

Show/hideArchitectures

These ARM instructions are available in all architectures.

These 32-bit Thumb instructions are available in ARMv6T2 and above.

These 16-bit Thumb instructions are available in ARMv4T and above.

There is no 16-bit Thumb RRX instruction.

Show/hideExamples

    ASR     r7, r8, r9
    LSLS    r1, r2, r3
    LSR     r4, r5, r6
    ROR     r4, r5, r6

Show/hideSee also

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