Exception return, without popping anything from the stack.
Syntax
SUBS{cond} pc, lr, #imm ; ARM and Thumb code
MOVS{cond} pc, lr ; ARM and Thumb code
op1S{cond} pc, Rn, #imm; ARM code only and is deprecated
op1S{cond} pc, Rn, Rm{,shift} ; ARM code only and is deprecated
op2S{cond} pc, #imm; ARM code only and is deprecated
op2S{cond} pc, Rm{,shift} ; ARM code only and is deprecated
where:
op1is one of
ADC,ADD,AND,BIC,EOR,ORN,ORR,RSB,RSC,SBC, andSUB.op2is one of
MOVandMVN.condis an optional condition code.
immis an immediate value. In Thumb code, it is limited to the range 0-255. In ARM code, it is a flexible second operand.
Rnis the first operand register. ARM deprecates the use of any register except
LR.Rmis the optionally shifted second or only operand register.
shiftis an optional condition code.
SUBS pc, lr, # subtracts
a value from the link register and loads the PC with the result,
then copies the SPSR to the CPSR.imm
You can use SUBS pc, lr, # to
return from an exception if there is no return state on the stack. The
value of imm# depends
on the exception to return from.imm
SUBS pc, lr, # writes
an address to the PC. The alignment of this address must be correct for
the instruction set in use after the exception return:imm
For a return to ARM, the address written to the PC must be word-aligned.
For a return to Thumb, the address written to the PC must be halfword-aligned.
For a return to Jazelle, there are no alignment restrictions on the address written to the PC.
The results of breaking these rules are unpredictable. However, no special precautions are required in software, if the instructions are used to return after a valid exception entry mechanism.
In Thumb, only SUBS{ is a valid instruction. cond}
pc, lr, #immMOVS
pc, lr is a synonym of SUBS pc, lr, #0. Other
instructions are undefined.
In ARM, only SUBS{ and cond} pc,
lr, #immMOVS{ are valid instructions. Other instructions are deprecated
in ARMv6T2 and above.cond}
pc, lr
Caution
Do not use these instructions in User mode or System mode. The effect of such an instruction is unpredictable, but the assembler cannot warn you at assembly time.
This ARM instruction is available in all versions of the ARM architecture.
This 32-bit Thumb instruction is available in ARMv6T2 and above, except the ARMv7-M architecture.
There is no 16-bit Thumb version of this instruction.
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