VLDR pseudo-instruction

The VLDR pseudo-instruction loads a constant value into every element of a 64-bit NEON vector, or into a VFP single-precision or double-precision register.

Note

This section describes the VLDR pseudo-instruction only.

Show/hideSyntax

VLDR{cond}.datatype Dd,=constant
VLDR{cond}.datatype Sd,=constant

where:

datatype

must be one of:

In

NEON only

Sn

NEON only

Un

NEON only

F32

NEON or VFP

F64

VFP only

n

must be one of 8, 16, 32, or 64.

cond

is an optional condition code.

Dd or Sd

is the extension register to be loaded.

constant

is an immediate value of the appropriate type for datatype.

Show/hideUsage

If an instruction (for example, VMOV) is available that can generate the constant directly into the register, the assembler uses it. Otherwise, it generates a doubleword literal pool entry containing the constant and loads the constant using a VLDR instruction.

Show/hideSee also

Concepts

Using the Assembler:

Reference
Copyright © 2010-2012 ARM. All rights reserved.ARM DUI 0489H
Non-ConfidentialID070912