ARM® Compiler toolchain Assembler Reference

Version 5.02


List of Topics

Conventions and feedback
Assembler command line options
Assembler command line syntax
Assembler command line options
--16
--32
--apcs=qualifier…qualifier
--arm
--arm_only
--bi
--bigend
--brief_diagnostics
--checkreglist
--compatible=name
--cpreproc
--cpreproc_opts=options
--cpu=list
--cpu=name
--debug
--depend=dependfile
--depend_format=string
--device=list
--device=name
--diag_error=tag{, tag}
--diag_remark=tag{, tag}
--diag_style=style
--diag_suppress=tag{, tag}
--diag_warning=tag{, tag}
--dllexport_all
--dwarf2
--dwarf3
--errors=errorfile
--execstack
--exceptions
--exceptions_unwind
--fpmode=model
--fpu=list
--fpu=name
-g
--help
-idir{,dir, …}
--keep
--length=n
--li
--library_type=lib
--licretry
--list=file
--list=
--littleend
-m
--maxcache=n
--md
--no_code_gen
--no_esc
--no_execstack
--no_exceptions
--no_exceptions_unwind
--no_hide_all
--no_project
--no_reduce_paths
--no_regs
--no_terse
--no_unaligned_access
--no_warn
-o filename
--pd
--predefine "directive"
--project=filename
--reduce_paths
--regnames=none
--regnames=callstd
--regnames=all
--reinitialize_workdir
--report-if-not-wysiwyg
--show_cmdline
--split_ldm
--thumb
--thumbx
--unaligned_access
--unsafe
--untyped_local_labels
--version_number
--via=file
--vsn
--width=n
--workdir=directory
--xref
ARM and Thumb Instructions
Instruction summary
Instruction width specifiers
Memory access instructions
General data processing instructions
Flexible second operand (Operand2)
Operand2 as a constant
Operand2 as a register with optional shift
Shift operations
Multiply instructions
Saturating instructions
Parallel instructions
Parallel add and subtract
Packing and unpacking instructions
Branch and control instructions
Coprocessor instructions
Miscellaneous instructions
ThumbEE instructions
Pseudo-instructions
Condition codes
ADD, SUB, RSB, ADC, SBC, and RSC
ADR (PC-relative)
ADR (register-relative)
ADRL pseudo-instruction
AND, ORR, EOR, BIC, and ORN
ASR, LSL, LSR, ROR, and RRX
B, BL, BX, BLX, and BXJ
BFC and BFI
BKPT
CBZ and CBNZ
CDP and CDP2
CHKA
CLREX
CLZ
CMP and CMN
CPS
CPY pseudo-instruction
DBG
DMB, DSB, and ISB
ENTERX and LEAVEX
ERET
HB, HBL, HBLP, and HBP
IT
LDC, LDC2, STC, and STC2
LDM and STM
LDR and STR (immediate offset)
LDR and STR (register offset)
LDR and STR, unprivileged
LDR (PC-relative)
LDR (register-relative)
LDR pseudo-instruction
LDREX and STREX
MAR and MRA
MCR, MCR2, MCRR, and MCRR2
MIA, MIAPH, and MIAxy
MOV and MVN
MOV32 pseudo-instruction
MOVT
MRC, MRC2, MRRC and MRRC2
MRS (system coprocessor register to ARM register)
MRS (PSR to general-purpose register)
MSR (ARM register to system coprocessor register)
MSR (general-purpose register to PSR)
MUL, MLA, and MLS
NEG pseudo-instruction
NOP
PKHBT and PKHTB
PLD, PLDW, and PLI
PUSH and POP
QADD, QSUB, QDADD, and QDSUB
REV, REV16, REVSH, and RBIT
RFE
SBFX and UBFX
SDIV and UDIV
SEL
SETEND
SEV, WFE, WFI, and YIELD
SMC
SMLAD and SMLSD
SMLALxy
SMLALD and SMLSLD
SMMUL, SMMLA, and SMMLS
SMUAD{X} and SMUSD{X}
SMULxy and SMLAxy
SMULWy and SMLAWy
SRS
SSAT and USAT
SSAT16 and USAT16
SUBS pc, lr
SVC
SWP and SWPB
SXT, SXTA, UXT, and UXTA
SYS
TBB and TBH
TST and TEQ
UMAAL
UMULL, UMLAL, SMULL, and SMLAL
UND pseudo-instruction
USAD8 and USADA8
NEON and VFP Programming
Instruction summary
Instructions shared by NEON and VFP
NEON logical and compare operations
NEON general data processing instructions
NEON shift instructions
NEON general arithmetic instructions
NEON multiply instructions
NEON load and store element and structure instructions
Interleaving provided by load and store, element and structure instructions
Alignment restrictions in load and store, element and structure instructions
NEON and VFP pseudo-instructions
VFP instructions
V{Q}{R}SHL (by signed variable)
V{Q}ABS and V{Q}NEG
V{Q}ADD, VADDL, VADDW, V{Q}SUB, VSUBL, and VSUBW
V{R}ADDHN and V{R}SUBHN
V{R}HADD and VHSUB
V{R}SHR (by immediate)
V{R}SHRN (by immediate)
V{R}SRA (by immediate)
VABA{L} and VABD{L}
VABS, VNEG, and VSQRT
VACGE and VACGT
VACLE and VACLT
VADD, VSUB, and VDIV
VAND, VBIC, VEOR, VORN, and VORR (register)
VAND and VORN (immediate)
VBIC and VORR (immediate)
VBIF, VBIT, and VBSL
VCEQ, VCGE, VCGT, VCLE, and VCLT
VCLE and VCLT
VCLS, VCLZ, and VCNT
VCMP
VCVT (between fixed-point or integer, and floating-point)
VCVT (between half-precision and single-precision floating-point)
VCVT (between single-precision and double-precision)
VCVT (between floating-point and integer)
VCVT (between floating-point and fixed-point)
VCVTB, VCVTT (half-precision extension)
VDUP
VEXT
VFMA, VFMS
VFMA, VFMS, VFNMA, VFNMS
VLDM, VSTM, VPOP, and VPUSH
VLDn and VSTn (single n-element structure to one lane)
VLDn (single n-element structure to all lanes)
VLDn and VSTn (multiple n-element structures)
VLDR pseudo-instruction
VLDR and VSTR (post-increment and pre-decrement)
VLDR and VSTR
VMAX, VMIN, VPMAX, and VPMIN
VMOV
VMOV, VMVN (immediate)
VMOV, VMVN (register)
VMOV (between two ARM registers and an extension register)
VMOV (between an ARM register and a NEON scalar)
VMOV (between one ARM register and single precision VFP)
VMOV2
VMOVL, V{Q}MOVN, VQMOVUN
VMRS and VMSR
VMUL, VMLA, VMLS, VNMUL, VNMLA, and VNMLS
VMUL{L}, VMLA{L}, and VMLS{L}
VMUL{L}, VMLA{L}, and VMLS{L} (by scalar)
VPADD{L}, VPADAL
VQ{R}DMULH (by vector or by scalar)
VQ{R}SHR{U}N (by immediate)
VQDMULL, VQDMLAL, and VQDMLSL (by vector or by scalar)
VRECPE and VRSQRTE
VRECPS and VRSQRTS
VREV
VSHL, VQSHL, VQSHLU, and VSHLL (by immediate)
VSLI and VSRI
VSWP
VTBL, VTBX
VTRN
VTST
VUZP, VZIP
Wireless MMX Technology Instructions
About Wireless MMX Technology instructions
ARM support for Wireless MMX Technology
Directives, WRN and WCN, to support Wireless MMX Technology
Frame directives and Wireless MMX Technology
Wireless MMX load and store instructions
Wireless MMX Technology and XScale instructions
Wireless MMX instructions
Wireless MMX pseudo-instructions
Directives Reference
Alphabetical list of directives
Symbol definition directives
Data definition directives
About assembly control directives
About frame directives
Reporting directives
Instruction set and syntax selection directives
Miscellaneous directives
ALIAS
ALIGN
AREA
ARM, THUMB, THUMBX, CODE16 and CODE32
ASSERT
ATTR
CN
COMMON
CP
DATA
DCB
DCD and DCDU
DCDO
DCFD and DCFDU
DCFS and DCFSU
DCI
DCQ and DCQU
DCW and DCWU
END
ENTRY
EQU
EXPORT or GLOBAL
EXPORTAS
FRAME ADDRESS
FRAME POP
FRAME PUSH
FRAME REGISTER
FRAME RESTORE
FRAME RETURN ADDRESS
FRAME SAVE
FRAME STATE REMEMBER
FRAME STATE RESTORE
FRAME UNWIND ON
FRAME UNWIND OFF
FUNCTION or PROC
ENDFUNC or ENDP
FIELD
GBLA, GBLL, and GBLS
GET or INCLUDE
IF, ELSE, ENDIF, and ELIF
IMPORT and EXTERN
INCBIN
INFO
KEEP
LCLA, LCLL, and LCLS
LTORG
MACRO and MEND
MAP
MEXIT
NOFP
OPT
QN, DN, and SN
RELOC
REQUIRE
REQUIRE8 and PRESERVE8
RLIST
RN
ROUT
SETA, SETL, and SETS
SPACE or FILL
TTL and SUBT
WHILE and WEND
Revisions for Assembler Reference

List of Tables

1. Compatible processor or architecture combinations
2. Severity of diagnostic messages
3. Specifying a command-line option and an AREA directive for GNU-stack sections
4. Location of instructions
5. Condition code suffixes
6. PC-relative offsets
7. register-relative offsets
8. Branch instruction availability and range
9. Offsets and architectures, LDR/STR, word, halfword, and byte
10. Options and architectures, LDR/STR (register offsets)
11. Offsets and architectures, LDR/STR (User mode)
12. PC-relative offsets
13. register-relative offsets
14. Range and encoding of expr
15. Location of NEON instructions
16. Location of shared NEON and VFP instructions
17. Location of VFP instructions
18. Patterns for immediate value
19. Permitted combinations of parameters
20. Permitted combinations of parameters
21. Permitted combinations of parameters
22. Available immediate values
23. Results for out-of-range inputs
24. Results for out-of-range inputs
25. Operation of doubleword VZIP.8
26. Operation of quadword VZIP.32
27. Operation of doubleword VUZP.8
28. Operation of quadword VUZP.32
29. Wireless MMX Technology instructions
30. Wireless MMX Technology pseudo-instructions
31. Location of directives
32. OPT directive settings
33. Differences between issue G and issue H
34. Differences between issue F and issue G
35. Differences between issue E and issue F
36. Differences between issue D and issue E
37. Differences between issue C and issue D
38. Differences between issue B and issue C
39. Differences between issue A and issue B

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Confidentiality Status

This document is Non-Confidential. The right to use, copy and disclose this document may be subject to license restrictions in accordance with the terms of the agreement entered into by ARM and the party that ARM delivered this document to.

Product Status

The information in this document is final, that is for a developed product.

Revision History
Revision AMay 2010ARM Compiler toolchain v4.1 Release
Revision B30 September 2010Update 1 for ARM Compiler toolchain v4.1
Revision C28 January 2011Update 2 for ARM Compiler toolchain v4.1 Patch 3
Revision D30 April 2011ARM Compiler toolchain v5.0 Release
Revision E29 July 2011Update 1 for ARM Compiler toolchain v5.0
Revision F30 September 2011ARM Compiler toolchain v5.01 Release
Revision G29 February 2012Document update 1 for ARM Compiler toolchain v5.01 Release
Revision H27 July 2012ARM Compiler toolchain v5.02 Release
Copyright © 2010-2012 ARM. All rights reserved.ARM DUI 0489H
Non-ConfidentialID070912