ARM® Compiler toolchain Assembler Reference

Version 5.03


List of Topics

Conventions and feedback
Assembler command-line options
Assembler command-line syntax
Assembler command-line options
--16
--32
--apcs=qualifier…qualifier
--arm
--arm_only
--bi
--bigend
--brief_diagnostics
--checkreglist
--compatible=name
--cpreproc
--cpreproc_opts=options
--cpu=list
--cpu=name
--debug
--depend=dependfile
--depend_format=string
--device=list
--device=name
--diag_error=tag{, tag}
--diag_remark=tag{, tag}
--diag_style=style
--diag_suppress=tag{, tag}
--diag_warning=tag{, tag}
--dllexport_all
--dwarf2
--dwarf3
--errors=errorfile
--execstack
--exceptions
--exceptions_unwind
--fpmode=model
--fpu=list
--fpu=name
-g
--help
-idir{,dir, …}
--keep
--length=n
--li
--library_type=lib
--licretry
--list=file
--list=
--littleend
-m
--maxcache=n
--md
--no_code_gen
--no_esc
--no_execstack
--no_exceptions
--no_exceptions_unwind
--no_hide_all
--no_project
--no_reduce_paths
--no_regs
--no_terse
--no_unaligned_access
--no_warn
-o filename
--pd
--predefine "directive"
--project=filename
--reduce_paths
--regnames=none
--regnames=callstd
--regnames=all
--reinitialize_workdir
--report-if-not-wysiwyg
--show_cmdline
--split_ldm
--thumb
--thumbx
--unaligned_access
--unsafe
--untyped_local_labels
--version_number
--via=file
--vsn
--width=n
--workdir=directory
--xref
ARM and Thumb Instructions
ARM and Thumb instruction summary
Instruction width specifiers
Memory access instructions
General data processing instructions
Flexible second operand (Operand2)
Operand2 as a constant
Operand2 as a register with optional shift
Shift operations
Multiply instructions
Saturating instructions
Parallel instructions
Parallel add and subtract
Packing and unpacking instructions
Branch and control instructions
Coprocessor instructions
Miscellaneous instructions
Pseudo-instructions
Condition codes
ADC
ADD
ADR (PC-relative)
ADR (register-relative)
ADRL pseudo-instruction
AND
ASR
B
BFC
BFI
BIC
BKPT
BL
BLX
BX
BXJ
CBZ and CBNZ
CDP and CDP2
CLREX
CLZ
CMP and CMN
CPS
CPY pseudo-instruction
DBG
DMB
DSB
EOR
ERET
ISB
IT
LDC and LDC2
LDM
LDR (immediate offset)
LDR (PC-relative)
LDR (register offset)
LDR (register-relative)
LDR pseudo-instruction
LDR, unprivileged
LDREX
LSL
LSR
MAR
MCR and MCR2
MCRR and MCRR2
MIA, MIAPH, and MIAxy
MLA
MLS
MOV
MOV32 pseudo-instruction
MOVT
MRA
MRC and MRC2
MRRC and MRRC2
MRS (PSR to general-purpose register)
MRS (system coprocessor register to ARM register)
MSR (ARM register to system coprocessor register)
MSR (general-purpose register to PSR)
MUL
MVN
NEG pseudo-instruction
NOP
ORN (Thumb only)
ORR
PKHBT and PKHTB
PLD, PLDW, and PLI
POP
PUSH
QADD
QDADD
QDSUB
QSUB
RBIT
REV
REV16
REVSH
RFE
ROR
RRX
RSB
RSC
SBC
SBFX
SDIV
SEL
SETEND
SEV
SMC
SMLAxy
SMLAD
SMLAL
SMLALD
SMLALxy
SMLAWy
SMLSD
SMLSLD
SMMLA
SMMLS
SMMUL
SMUAD
SMULxy
SMULL
SMULWy
SMUSD
SRS
SSAT
SSAT16
STC and STC2
STM
STR (immediate offset)
STR (register offset)
STR, unprivileged
STREX
SUB
SUBS pc, lr
SVC
SWP and SWPB
SXTAB
SXTAB16
SXTAH
SXTB
SXTB16
SXTH
SYS
TBB and TBH
TEQ
TST
UBFX
UDIV
UMAAL
UMLAL
UMULL
UND pseudo-instruction
USAD8
USADA8
USAT
USAT16
UXTAB
UXTAB16
UXTAH
UXTB
UXTB16
UXTH
WFE
WFI
YIELD
ThumbEE Instructions
Instruction summary
ThumbEE instruction differences
CHKA
ENTERX and LEAVEX
HB, HBL, HBLP, and HBP
NEON and VFP Programming
NEON and VFP instruction summary
Instructions shared by NEON and VFP
NEON logical and compare operations
NEON general data processing instructions
NEON shift instructions
NEON general arithmetic instructions
NEON multiply instructions
NEON load and store element and structure instructions
Interleaving provided by load and store, element and structure instructions
Alignment restrictions in load and store, element and structure instructions
NEON and VFP pseudo-instructions
VFP instructions
VABA and VABAL
VABD and VABDL
VABS
VABS (floating-point)
VACLE, VACLT, VACGE and VACGT
VADD (floating-point)
VADD (integer)
VADDHN
VADDL and VADDW
VAND (immediate)
VAND (register)
VBIC (immediate)
VBIC (register)
VBIF
VBIT
VBSL
VCEQ (immediate #0)
VCEQ (register)
VCGE (immediate #0)
VCGE (register)
VCGT (immediate #0)
VCGT (register)
VCLE (immediate #0)
VCLE (register)
VCLS
VCLT (immediate #0)
VCLT (register)
VCLZ
VCMP, VCMPE
VCNT
VCVT (between fixed-point or integer, and floating-point)
VCVT (between half-precision and single-precision floating-point)
VCVT (between single-precision and double-precision)
VCVT (between floating-point and integer)
VCVT (between floating-point and fixed-point)
VCVTB, VCVTT (half-precision extension)
VDIV
VDUP
VEOR
VEXT
VFMA, VFMS
VFMA, VFMS, VFNMA, VFNMS
VHADD
VHSUB
VLDn (single n-element structure to one lane)
VLDn (single n-element structure to all lanes)
VLDn (multiple n-element structures)
VLDM
VLDR
VLDR (post-increment and pre-decrement)
VLDR pseudo-instruction
VMAX and VMIN
VMLA
VMLA (by scalar)
VMLA (floating-point)
VMLAL (by scalar)
VMLAL
VMLS (by scalar)
VMLS
VMLS (floating-point)
VMLSL
VMLSL (by scalar)
VMOV
VMOV (immediate)
VMOV (register)
VMOV (between one ARM register and single precision VFP)
VMOV (between two ARM registers and an extension register)
VMOV (between an ARM register and a NEON scalar)
VMOVL
VMOVN
VMOV2
VMRS
VMSR
VMUL
VMUL (floating-point)
VMUL (by scalar)
VMULL
VMULL (by scalar)
VMVN (register)
VMVN (immediate)
VNEG (floating-point)
VNEG
VNMLA (floating-point)
VNMLS (floating-point)
VNMUL (floating-point)
VORN (register)
VORN (immediate)
VORR (register)
VORR (immediate)
VPADAL
VPADD
VPADDL
VPMAX and VPMIN
VPOP
VPUSH
VQABS
VQADD
VQDMLAL and VQDMLSL (by vector or by scalar)
VQDMULH (by vector or by scalar)
VQDMULL (by vector or by scalar)
VQMOVN and VQMOVUN
VQNEG
VQRDMULH (by vector or by scalar)
VQRSHL (by signed variable)
VQRSHRN and VQRSHRUN (by immediate)
VQSHL (by signed variable)
VQSHL and VQSHLU (by immediate)
VQSHRN and VQSHRUN (by immediate)
VQSUB
VRADDHN
VRECPE
VRECPS
VREV16, VREV32, and VREV64
VRHADD
VRSHL (by signed variable)
VRSHR (by immediate)
VRSHRN (by immediate)
VRSQRTE
VRSQRTS
VRSRA (by immediate)
VRSUBHN
VSHL (by immediate)
VSHL (by signed variable)
VSHLL (by immediate)
VSHR (by immediate)
VSHRN (by immediate)
VSLI
VSQRT
VSRA (by immediate)
VSRI
VSTM
VSTn (multiple n-element structures)
VSTn (single n-element structure to one lane)
VSTR
VSTR (post-increment and pre-decrement)
VSUB (floating-point)
VSUB (integer)
VSUBHN
VSUBL and VSUBW
VSWP
VTBL and VTBX
VTRN
VTST
VUZP
VZIP
Wireless MMX Technology Instructions
About Wireless MMX Technology instructions
ARM support for Wireless MMX Technology
Directives, WRN and WCN, to support Wireless MMX Technology
Frame directives and Wireless MMX Technology
Wireless MMX load and store instructions
Wireless MMX Technology and XScale instructions
Wireless MMX instructions
Wireless MMX pseudo-instructions
Directives Reference
Alphabetical list of directives
Symbol definition directives
Data definition directives
About assembly control directives
About frame directives
Reporting directives
Instruction set and syntax selection directives
Miscellaneous directives
ALIAS
ALIGN
AREA
ARM, THUMB, THUMBX, CODE16 and CODE32
ASSERT
ATTR
CN
COMMON
CP
DATA
DCB
DCD and DCDU
DCDO
DCFD and DCFDU
DCFS and DCFSU
DCI
DCQ and DCQU
DCW and DCWU
END
ENTRY
EQU
EXPORT or GLOBAL
EXPORTAS
FRAME ADDRESS
FRAME POP
FRAME PUSH
FRAME REGISTER
FRAME RESTORE
FRAME RETURN ADDRESS
FRAME SAVE
FRAME STATE REMEMBER
FRAME STATE RESTORE
FRAME UNWIND ON
FRAME UNWIND OFF
FUNCTION or PROC
ENDFUNC or ENDP
FIELD
GBLA, GBLL, and GBLS
GET or INCLUDE
IF, ELSE, ENDIF, and ELIF
IMPORT and EXTERN
INCBIN
INFO
KEEP
LCLA, LCLL, and LCLS
LTORG
MACRO and MEND
MAP
MEXIT
NOFP
OPT
QN, DN, and SN
RELOC
REQUIRE
REQUIRE8 and PRESERVE8
RLIST
RN
ROUT
SETA, SETL, and SETS
SPACE or FILL
TTL and SUBT
WHILE and WEND
Revisions for Assembler Reference

List of Tables

1. Compatible processor or architecture combinations
2. Severity of diagnostic messages
3. Specifying a command-line option and an AREA directive for GNU-stack sections
4. Location of instructions
5. Condition code suffixes
6. PC-relative offsets
7. register-relative offsets
8. Branch instruction availability and range
9. Branch instruction availability and range
10. Branch instruction availability and range
11. Branch instruction availability and range
12. Branch instruction availability and range
13. Offsets and architectures, LDR, word, halfword, and byte
14. PC-relative offsets
15. Options and architectures, LDR (register offsets)
16. Register-relative offsets
17. Offsets and architectures, LDR (User mode)
18. Offsets and architectures, STR, word, halfword, and byte
19. Options and architectures, STR (register offsets)
20. Offsets and architectures, STR (User mode)
21. Range and encoding of expr
22. Location of additional ThumbEE instructions
23. ThumbEE LDR/STR (immediate offset) offsets and availability
24. ThumbEE LDR/STR (register offset) offsets and availability
25. ThumbEE LDR (register-relative) offsets
26. Location of NEON instructions
27. Location of shared NEON and VFP instructions
28. Location of VFP instructions
29. Patterns for immediate value
30. Permitted combinations of parameters
31. Permitted combinations of parameters
32. Permitted combinations of parameters
33. Available immediate values
34. Available immediate values
35. Patterns for immediate value
36. Available immediate ranges
37. Available immediate ranges
38. Available immediate ranges
39. Results for out-of-range inputs
40. Results for out-of-range inputs
41. Available immediate ranges
42. Available immediate ranges
43. Results for out-of-range inputs
44. Results for out-of-range inputs
45. Available immediate ranges
46. Available immediate ranges
47. Available immediate ranges
48. Available immediate ranges
49. Available immediate ranges
50. Available immediate ranges
51. Permitted combinations of parameters
52. Permitted combinations of parameters
53. Operation of doubleword VUZP.8
54. Operation of quadword VUZP.32
55. Operation of doubleword VZIP.8
56. Operation of quadword VZIP.32
57. Wireless MMX Technology instructions
58. Wireless MMX Technology pseudo-instructions
59. Location of directives
60. OPT directive settings
61. Differences between issue H and issue I
62. Differences between issue G and issue H
63. Differences between issue F and issue G
64. Differences between issue E and issue F
65. Differences between issue D and issue E
66. Differences between issue C and issue D
67. Differences between issue B and issue C
68. Differences between issue A and issue B

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This document is intended only to assist the reader in the use of the product. ARM shall not be liable for any loss or damage arising from the use of any information in this document, or any error or omission in such information, or any incorrect use of the product.

Where the term ARM is used it means “ARM or any of its subsidiaries as appropriate”.

Confidentiality Status

This document is Non-Confidential. The right to use, copy and disclose this document may be subject to license restrictions in accordance with the terms of the agreement entered into by ARM and the party that ARM delivered this document to.

Product Status

The information in this document is final, that is for a developed product.

Revision History
Revision AMay 2010ARM Compiler toolchain v4.1 Release
Revision B30 September 2010Update 1 for ARM Compiler toolchain v4.1
Revision C28 January 2011Update 2 for ARM Compiler toolchain v4.1 Patch 3
Revision D30 April 2011ARM Compiler toolchain v5.0 Release
Revision E29 July 2011Update 1 for ARM Compiler toolchain v5.0
Revision F30 September 2011ARM Compiler toolchain v5.01 Release
Revision G29 February 2012Document update 1 for ARM Compiler toolchain v5.01 Release
Revision H27 July 2012ARM Compiler toolchain v5.02 Release
Revision I31 January 2013ARM Compiler toolchain v5.03 Release
Copyright © 2010-2013 ARM. All rights reserved.ARM DUI 0489I
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