3.6.1. B, BL, BX, and BLX

Branch instructions.

Syntax

B{cond} label
BL label
BX Rm
BLX Rm

where:

cond

is an optional condition code, see Conditional execution.

label

is a PC-relative expression. See PC‑relative expressions.

Rm

is a register providing the address to branch to.

Operation

All these instructions cause a branch to the address indicated by label or contained in the register specified by Rm. In addition:

  • The BL and BLX instructions write the address of the next instruction to LR, the link register R14.

  • The BX and BLX instructions result in a HardFault exception if bit[0] of Rm is 0.

BL and BLX instructions also set bit[0] of the LR to 1. This ensures that the value is suitable for use by a subsequent POP {PC} or BX instruction to perform a successful return branch.

Table 3.9 shows the ranges for the various branch instructions.

Table 3.9. Branch ranges

InstructionBranch range
B label−2KB to +2KB
Bcond label−256 bytes to +254 bytes
BL label−16MB to +16MB
BX RmAny value in register
BLX RmAny value in register

Restrictions

In these instructions:

  • Do not use SP or PC in the BX or BLX instruction.

  • For BX and BLX, bit[0] of Rm must be 1 for correct execution. Bit[0] is used to update the EPSR T-bit and is discarded from the target address.

Note

Bcond is the only conditional instruction on the Cortex-M0 processor.

Condition flags

These instructions do not change the flags.

Examples

    B      loopA  ; Branch to loopA
    BL     funC   ; Branch with link (Call) to function funC, return address
                  ; stored in LR
    BX     LR     ; Return from function call
    BLX    R0     ; Branch with link and exchange (Call) to a address stored
                  ; in R0
    BEQ    labelD ; Conditionally branch to labelD if last flag setting
                  ; instruction set the Z flag, else do not branch.

Copyright © 2009 ARM Limited. All rights reserved.ARM DUI 0497A
Non-Confidential