3.5.1. ADC, ADD, RSB, SBC, and SUB

Add with carry, Add, Reverse Subtract, Subtract with carry, and Subtract.

Note

Cortex-M0 supports the ADC, RSB, and SBC instructions only as instructions that update the flags, that is, as ADCS, RSBS, and SBCS.

Syntax

ADCS   {Rd,} Rn, Rm
ADD{S} {Rd,} Rn, <Rm|#imm>
RSBS   {Rd,} Rn, Rm, #0
SBCS   {Rd,} Rn, Rm
SUB{S} {Rd,} Rn, <Rm|#imm>

Where:

S

causes an ADD or SUB instruction to update flags

Rd

specifies the result register

Rn

specifies the first source register

Rm

specifies the second source register

imm

specifies a constant immediate value.

When the optional Rd register specifier is omitted, it is assumed to take the same value as Rn, for example ADDS R1,R2 is identical to ADDS R1,R1,R2.

Operation

The ADCS instruction adds the value in Rn to the value in Rm, adding a further one if the carry flag is set, places the result in the register specified by Rd and updates the N, Z, C, and V flags.

The ADD instruction adds the value in Rn to the value in Rm or an immediate value specified by imm and places the result in the register specified by Rd.

The ADDS instruction performs the same operation as ADD and also updates the N, Z, C and V flags.

The RSBS instruction subtracts the value in Rn from zero, producing the arithmetic negative of the value, and places the result in the register specified by Rd and updates the N, Z, C and V flags.

The SBCS instruction subtracts the value of Rm from the value in Rn, deducts a further one if the carry flag is set. It places the result in the register specified by Rd and updates the N, Z, C and V flags.

The SUB instruction subtracts the value in Rm or the immediate specified by imm. It places the result in the register specified by Rd.

The SUBS instruction performs the same operation as SUB and also updates the N, Z, C and V flags.

Use ADC and SBC to synthesize multiword arithmetic, see Examples.

See also ADR.

Restrictions

Table 3.7 lists the legal combinations of register specifiers and immediate values that can be used with each instruction.

Table 3.7. ADC, ADD, RSB, SBC and SUB operand restrictions

InstructionRdRnRmimmRestrictions
ADCSR0-R7R0-R7R0-R7-

Rd and Rn must specify the same register.

ADDR0-R15R0-R15R0-R15-

Rd and Rn must specify the same register.

Rn and Rm must not both specify the PC (R15).

R0-R7SP or PC-0-1020

Immediate value must be an integer multiple of four.

SPSP-0-508

Immediate value must be an integer multiple of four.

ADDSR0-R7R0-R7-0-7-
R0-R7R0-R7-0-255

Rd and Rn must specify the same register.

R0-R7R0-R7R0-R7--
RSBSR0-R7R0-R7---
SBCSR0-R7R0-R7R0-R7-

Rd and Rn must specify the same register.

SUBSPSP-0-508

Immediate value must be an integer multiple of four.

SUBSR0-R7R0-R7-0-7-
R0-R7R0-R7-0-255

Rd and Rn must specify the same register.

R0-R7R0-R7R0-R7--

Examples

Example 3.1 shows two instructions that add a 64-bit integer contained in R0 and R1 to another 64-bit integer contained in R2 and R3, and place the result in R0 and R1.

Example 3.1. 64-bit addition

    ADDS    R0, R0, R2    ; add the least significant words
    ADCS    R1, R1, R3    ; add the most significant words with carry

Multiword values do not have to use consecutive registers. Example 3.2 shows instructions that subtract a 96-bit integer contained in R1, R2, and R3 from another contained in R4, R5, and R6. The example stores the result in R4, R5, and R6.

Example 3.2. 96-bit subtraction

    SUBS    R4, R4, R1    ; subtract the least significant words
    SBCS    R5, R5, R2    ; subtract the middle words with carry
    SBCS    R6, R6, R3    ; subtract the most significant words with carry

Example 3.3 shows the RSBS instruction used to perform a 1's complement of a single register.

Example 3.3.  Arithmetic negation

    RSBS    R7, R7, #0    ; subtract R7 from zero

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