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Add with carry, Add, Reverse Subtract, Subtract with carry, and Subtract.
CortexM0 supports the ADC
, RSB
,
and SBC
instructions only as instructions that update the
flags, that is, as ADCS
, RSBS
, and SBCS
.
ADCS {Rd
,}Rn
,Rm
ADD{S} {Rd
,}Rn
,<Rm#imm>
RSBS {Rd
,}Rn
,Rm
,#0
SBCS {Rd
,}Rn
,Rm
SUB{S} {Rd
,}Rn
,<
Rm
#imm
>
Where:
S
causes an ADD
or SUB
instruction
to update flags
Rd
specifies the result register
Rn
specifies the first source register
Rm
specifies the second source register
imm
specifies a constant immediate value.
When the optional Rd
register specifier
is omitted, it is assumed to take the same value as
,
for example Rn
ADDS R1,R2
is identical to ADDS R1,R1,R2
.
The ADCS
instruction adds the value in
to
the value in Rn
,
adding a further one if the carry flag is set, places the result
in the register specified by Rm
Rd
and updates
the N, Z, C, and V flags.
The ADD
instruction adds the value in
to
the value in Rn
or
an immediate value specified by Rm
and
places the result in the register specified by imm
Rd
.
The ADDS
instruction performs the same operation
as ADD
and also updates the N, Z, C and V flags.
The RSBS
instruction subtracts the value in
from
zero, producing the arithmetic negative of the value, and places
the result in the register specified by Rd and updates the N, Z,
C and V flags.Rn
The SBCS
instruction subtracts the value of
from
the value in Rm
,
deducts a further one if the carry flag is set. It places the result
in the register specified by Rd and updates the N, Z, C and V flags.Rn
The SUB
instruction subtracts the value in
or
the immediate specified by Rm
imm
. It places the
result in the register specified by Rd
.
The SUBS
instruction performs the same operation
as SUB
and also updates the N, Z, C and V flags.
Use ADC
and SBC
to
synthesize multiword arithmetic, see Examples.
See also ADR.
Table 3.7 lists the legal combinations of register specifiers and immediate values that can be used with each instruction.
Table 3.7. ADC, ADD, RSB, SBC and SUB operand restrictions
Instruction  Rd  Rn  Rm  imm  Restrictions 

ADCS  R0R7  R0R7  R0R7   

ADD  R0R15  R0R15  R0R15   

R0R7  SP or PC    01020  Immediate value must be an integer multiple of four.  
SP  SP    0508  Immediate value must be an integer multiple of four.  
ADDS  R0R7  R0R7    07   
R0R7  R0R7    0255 
 
R0R7  R0R7  R0R7      
RSBS  R0R7  R0R7       
SBCS  R0R7  R0R7  R0R7   

SUB  SP  SP    0508  Immediate value must be an integer multiple of four. 
SUBS  R0R7  R0R7    07   
R0R7  R0R7    0255 
 
R0R7  R0R7  R0R7     
Example 3.1 shows two
instructions that add a 64bit integer contained in R0 and R1 to another
64bit integer contained in R2 and R3, and place the result in R0
and R1
.
Example 3.1. 64bit addition
ADDS R0, R0, R2 ; add the least significant words ADCS R1, R1, R3 ; add the most significant words with carry
Multiword values do not have to use consecutive registers. Example 3.2 shows instructions that subtract a 96bit integer contained in R1, R2, and R3 from another contained in R4, R5, and R6. The example stores the result in R4, R5, and R6.
Example 3.2. 96bit subtraction
SUBS R4, R4, R1 ; subtract the least significant words SBCS R5, R5, R2 ; subtract the middle words with carry SBCS R6, R6, R3 ; subtract the most significant words with carry
Example 3.3 shows the RSBS
instruction
used to perform a 1's complement of a single register.