3.4. Memory access instructions

Table 3.5 shows the memory access instructions:

Table 3.5. Memory access instructions

MnemonicBrief descriptionSee
ADRGenerate PC-relative addressADR
LDMLoad Multiple registersLDM and STM
LDR{type}Load Register using immediate offsetLDR and STR, immediate offset
LDR{type}Load Register using register offsetLDR and STR, register offset
LDRLoad Register from PC-relative addressLDR, PC‑relative
POPPop registers from stackPUSH and POP
PUSHPush registers onto stackPUSH and POP
STMStore Multiple registersLDM and STM
STR{type}Store Register using immediate offsetLDR and STR, immediate offset
STR{type}Store Register using register offsetLDR and STR, register offset

Copyright © 2009 ARM Limited. All rights reserved.ARM DUI 0497A
Non-Confidential