Cortex™-M0 Devices Generic User Guide

Table of Contents

About this book
Product revision status
Intended audience
Using this book
Typographical conventions
Additional reading
Feedback on this product
Feedback on content
1. Introduction
1.1. About the Cortex-M0 processor and core peripherals
1.1.1. System-level interface
1.1.2. Optional integrated configurable debug
1.1.3. Cortex-M0 processor features summary
1.1.4. Cortex-M0 core peripherals
2. The Cortex-M0 Processor
2.1. Programmers model
2.1.1. Processor modes
2.1.2. Stacks
2.1.3. Core registers
2.1.4. Exceptions and interrupts
2.1.5. Data types
2.1.6. The Cortex Microcontroller Software Interface Standard
2.2. Memory model
2.2.1. Memory regions, types and attributes
2.2.2. Memory system ordering of memory accesses
2.2.3. Behavior of memory accesses
2.2.4. Software ordering of memory accesses
2.2.5. Memory endianness
2.3. Exception model
2.3.1. Exception states
2.3.2. Exception types
2.3.3. Exception handlers
2.3.4. Vector table
2.3.5. Exception priorities
2.3.6. Exception entry and return
2.4. Fault handling
2.4.1. Lockup
2.5. Power management
2.5.1. Entering sleep mode
2.5.2. Wakeup from sleep mode
2.5.3. The optional Wakeup Interrupt Controller
2.5.4. The external event signal
2.5.5. Power management programming hints
3. The Cortex-M0 Instruction Set
3.1. Instruction set summary
3.2. Intrinsic functions
3.3. About the instruction descriptions
3.3.1. Operands
3.3.2. Restrictions when using PC or SP
3.3.3. Shift Operations
3.3.4. Address alignment
3.3.5. PC‑relative expressions
3.3.6. Conditional execution
3.4. Memory access instructions
3.4.1. ADR
3.4.2. LDR and STR, immediate offset
3.4.3. LDR and STR, register offset
3.4.4. LDR, PC‑relative
3.4.5. LDM and STM
3.4.6. PUSH and POP
3.5. General data processing instructions
3.5.1. ADC, ADD, RSB, SBC, and SUB
3.5.2. AND, ORR, EOR, and BIC
3.5.3. ASR, LSL, LSR, and ROR
3.5.4. CMP and CMN
3.5.5. MOV and MVN
3.5.6. MULS
3.5.7. REV, REV16, and REVSH
3.5.8. SXT and UXT
3.5.9. TST
3.6. Branch and control instructions
3.6.1. B, BL, BX, and BLX
3.7. Miscellaneous instructions
3.7.1. BKPT
3.7.2. CPS
3.7.3. DMB
3.7.4. DSB
3.7.5. ISB
3.7.6. MRS
3.7.7. MSR
3.7.8. NOP
3.7.9. SEV
3.7.10. SVC
3.7.11. WFE
3.7.12. WFI
4. Cortex-M0 Peripherals
4.1. About the Cortex-M0 peripherals
4.2. Nested Vectored Interrupt Controller
4.2.1. Accessing the Cortex-M0 NVIC registers using CMSIS
4.2.2. Interrupt Set-enable Register
4.2.3. Interrupt Clear-enable Register
4.2.4. Interrupt Set-pending Register
4.2.5. Interrupt Clear-pending Register
4.2.6. Interrupt Priority Registers
4.2.7. Level-sensitive and pulse interrupts
4.2.8. NVIC usage hints and tips
4.3. System Control Block
4.3.1. The CMSIS mapping of the Cortex-M0 SCB registers
4.3.2. CPUID Register
4.3.3. Interrupt Control and State Register
4.3.4. Application Interrupt and Reset Control Register
4.3.5. System Control Register
4.3.6. Configuration and Control Register
4.3.7. System Handler Priority Registers
4.3.8. SCB usage hints and tips
4.4. Optional system timer, SysTick
4.4.1. SysTick Control and Status Register
4.4.2. SysTick Reload Value Register
4.4.3. SysTick Current Value Register
4.4.4. SysTick Calibration Value Register
4.4.5. SysTick usage hints and tips
A. Cortex-M0 Options
A.1. Cortex-M0 implementation options

List of Figures

1.1. Cortex-M0 implementation
2.1. Vector table
3.1. ASR #3
3.2. LSR #3
3.3. LSL #3
3.4. ROR #3

List of Tables

2.1. Summary of processor mode and stack use options
2.2. Core register set summary
2.3. PSR register combinations
2.4. APSR bit assignments
2.5. IPSR bit assignments
2.6. EPSR bit assignments
2.7. PRIMASK register bit assignments
2.8. CONTROL register bit assignments
2.9. Memory access behavior
2.10. Memory region shareability and cache policies
2.11. Properties of the different exception types
2.12. Exception return behavior
3.1. Cortex-M0 instructions
3.2. CMSIS intrinsic functions to generate some Cortex-M0 instructions
3.3. CMSIS intrinsic functions to access the special registers
3.4. Condition code suffixes
3.5. Memory access instructions
3.6. Data processing instructions
3.7. ADC, ADD, RSB, SBC and SUB operand restrictions
3.8. Branch and control instructions
3.9. Branch ranges
3.10. Miscellaneous instructions
4.1. Core peripheral register regions
4.2. NVIC register summary
4.3. CMSIS access NVIC functions
4.4. ISER bit assignments
4.5. ICER bit assignments
4.6. ISPR bit assignments
4.7. ICPR bit assignments
4.8. IPR bit assignments
4.9. CMSIS functions for NVIC control
4.10. Summary of the SCB registers
4.11. CPUID register bit assignments
4.12. ICSR bit assignments
4.13. AIRCR bit assignments
4.14. SCR bit assignments
4.15. CCR bit assignments
4.16. System fault handler priority fields
4.17. SHPR2 register bit assignments
4.18. SHPR3 register bit assignments
4.19. System timer registers summary
4.20. SYST_CSR bit assignments
4.21. SYST_RVR bit assignments
4.22. SYST_CVR bit assignments
4.23. SYST_CALIB register bit assignments
A.1. Effects of the Cortex-M0 implementation options

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Product Status

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Revision History
Revision A08 October 2009First release
Copyright © 2009 ARM Limited. All rights reserved.ARM DUI 0497A