Debug hardware Advanced settings

Depending on your development platform configuration, a selection of the following controls is available in the Advanced settings:

Allow ICE to perform TAP reset

Set this item to True to allow your debug hardware unit to hold the nSRST line active long enough to perform any post-reset setup that might be required after a target-initiated reset. This can extend the time that the target is held in reset. If this item is set to False, your debug hardware unit does not assert the reset line, but post-reset setup might not be complete before the target starts to run.

Allow ICE to latch System Reset

Set this item to True to allow your debug hardware unit to perform nTRST reset while holding nSRST. This ensures that the Test Access Port (TAP) state machine and associated debug logic is properly reset.

LVDS Debug Interface mode

This can be set either to JTAG or SWD. If set to SWD, this causes RVI to connect to the target using the SWD protocol instead of JTAG.

nSRST High mode

Selects the drive strength used when the reset signal is in the high, or inactive, state. Output can be driven as a strong or weak high, or not driven (tri-state).

nTRST High mode

Selects the drive strength used when the reset signal is in the high, or inactive, state. Output can be driven as a strong or weak high, or not driven (tri-state).

nSRST Low mode

Selects the drive strength used when the reset signal is in the low, or active, state. Output can be driven as a strong or weak low, or not driven (tri-state).

nTRST Low mode

Selects the drive strength used when the reset signal is in the low, or active, state. Output can be driven as a strong or weak low, or not driven (tri-state).

nSRST Hold Time (ms)

Specifies how long the debug hardware unit holds the hardware nSRST system reset signal LOW.

nTRST Hold Time (ms)

Specifies how long the debug hardware unit holds the nTRST TAP reset signal LOW.

nSRST Post Reset Delay (ms)

Specifies how long after the hardware nSRST system reset before the debug hardware unit enters the Post Reset State.

nTRST Post Reset Delay (ms)

Specifies how long after the nTRST TAP reset before the debug hardware unit enters the Post Reset State.

Perform TAP reset on first connect

Resets the target hardware whenever you connect.

Perform SYS reset on first connect

Resets the target hardware by asserting the nSRST signal when connecting to the first device in a debug session.

Reset Type

One of the following:

nSRST

Resets the hardware by holding the hardware nSRST system reset signal LOW. This is the default.

nTRST

Resets the target TAP by holding the nTRST TAP reset signal LOW.

nSRST+nTRST

Resets the hardware and the target TAP by holding both the hardware nSRST system reset signal and the nTRST TAP reset signal LOW.

Fake

Resets the system by entering supervisor mode, and setting the program counter to the address of the reset vector (known as a soft reset).

Ctrl_Reg

The Control register. This reset, in instances where processors have a reset register, enables you to reset the processor without using the external reset lines. If you set the reset type to Ctrl_Reg, then this control register is used.

SWO Mode

Set to Manchester or UART, depending on the target mode.

If the SWO Mode is set to UART, the debug hardware unit is able to detect the SWO UART Baud rate.

This setting has no effect in Manchester mode.

SWO UART Baud rate

For the frequency of the incoming data. If you set this to 0, the system attempts to autodetect the baud rate.

Note

UART mode in the SWO context also means Non Return to Zero (NRZ) mode.

TAP Reset via State Transitions

If you want the JTAG logic in the target hardware to be reset by forcing transitions within its state machine. This is done in addition to holding the nTRST TAP reset signal LOW. Select this option if nTRST is not connected, or if the target hardware requires that you force a reset of the JTAG logic whenever resetting.

Target nSRST + nTRST linked

If the target hardware has its nSRST and nTRST JTAG signals linked.

Use SWJ Switching

If this is set, it causes the SWJ switching sequence to be sent before connecting to the target device. On devices that support SWJ switching, this causes the DAP to switch its interface to the selected protocol.

Use deprecated SWJ Sequence

If this is set, it causes your debug hardware unit to use an alternative SWJ switching sequence, used on some older SWD-compatible targets. This option is normally clear, unless the processor requires the deprecated sequence.

Note

For RVI, the LVDS Debug Interface mode, Use SWJ Switching, and Use deprecated SWJ Sequence controls are not present in the control pane if you are not using a Low Voltage Differential Signaling (LVDS) probe.

User Outputn

Used to set the state of the USER IO pins on the rear of the RVI unit, or on the front of the DSTREAM unit.

Show/hideSee also

Tasks
Reference

ARM® DSTREAM™ System and Interface Design Reference:

ARM® RVI™ and RVT™ System and Interface Design Reference:

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