Considerations when debugging processors with caches enabled

When debugging a processor with caches enabled, you might have to provide the address of an area of memory on the target that can be used exclusively by debug hardware. On some targets, the debug software downloads code sequences to this area to perform various tasks, such as cleaning the cache, and accessing the system registers. Debug hardware does not preserve the contents of this area.

A code sequence area is only required for certain processors where the required operations cannot be performed directly over JTAG. If debug hardware requires a code sequence area, and one has not been enabled, errors are displayed within the debugger. For example:


The code sequence area must be 128 bytes long and in a non-cacheable, readable and writeable area.

To set up a code sequence area, use the options for each specific processor in the RVConfig utility. This provides access to configuration items for each processor for:


These settings might also be available in your debugger Registers view. Any settings modified using the Registers view in your debugger are only modified for the duration of the debug session. Any settings modified using the RVConfig utility are persistent until modified again.

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