Cortex-M3 semihosting

Because Cortex-M3 does not provide vector catch on SVC, and the vector table contains jump addresses rather than instructions, semihosting cannot be supported using an SVC instruction.

As an alternative, semihosting is implemented using a specific software breakpoint that is recognized as a semihosting break by the debugger. The breakpoint instruction opcode contains an immediate 8-bit value. The C library uses the BKPT 0xAB opcode for semihosting. The debugger can test for this opcode pattern to determine if the breakpoint was a semihosting request or not.

When the semihosting break is executed, the semihosting call is processed in the normal way. After processing, execution continues from the instruction that follows the software breakpoint. The debugger does not stop on the breakpoint.

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