Strategies used by debug hardware to debug cached processors

When debugging a cached processor, debug hardware uses the following strategies.

On debug entry
  • Debug hardware forces Write-Through (WT) on processors that support this debug feature.

  • Debug hardware disables cache line fill on processors that support disabling of this feature in debug.

  • Debug hardware disables Translation Look-aside Buffer (TLB) loads on processors that support disabling of this feature in debug.

  • If data is read from cacheable memory, it is only read into the caches if, and only if, disable linefill is not possible.

  • TLB entries and caches remain enabled.

On data write
  • If WT is possible, nothing cache-related is performed.

  • If WT is not possible, the write depends on processor size and data size:

    1. Debug hardware can write to memory with caches enabled, and then write disabled, effectively simulating write through.

    2. Debug hardware can clean and invalidate the Dcache and disable it.


      The ARM940T processor requires that Code Sequences are enabled to do this.

On restart into debug
  • On processors that support the features, forced WT is removed, linefills are re-enabled, and TLB loads are enabled. If, and only if, data has been written, the Icache is invalidated. If, and only if, Dcache has been disabled, then it is re-enabled.

Data writes that could cause the cache operations described include user accesses using your debugger, downloads, and any software breakpoints present in the system.


For the ARM940T processor you must configure the code sequence settings before attempting to debug with caches enabled.

When the cache is enabled, the speed of semihosting decreases, because of the additional cache maintenance overhead performed by the debugger.

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