The use of DCC interrupts has significant speed implications when using Virtual Ethernet/TTY mode. If possible, you must tie DCC interrupts into the interrupt system of the target and be able to enable and disable the read and write interrupt individually.
Note
This is a configuration item that you must select when configuring the kernel, when using an ARM driver.
debug hardware uses JTAG to control debug operations, and JTAG is used to send and receive data over DCC. debug hardware polls the target JTAG for status:
If interrupts are used, the target is interrupted when data is written to the DCC register or read from it. This enables the target to deal quickly with the data, and continue normal processing.
If interrupts are not available, the target must regularly poll the DCC register for any new data. This means that the target wastes time checking the register for data when none is present. Subsequent data is only discovered at the next poll.
If debug hardware finds that there is data to be transferred into or out of DCC, it attempts to transfer as many words as possible in one burst, up to a predefined limit. However, if the target has not sent more data or emptied its transfer register, debug hardware breaks out of its burst and begins polling the execution status and DCC.
See also
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