CoreSight topology and associations for the Cortex-R4 FPGA

The following figure shows the CoreSight topology diagram for Cortex-R4 FPGA:

Figure 46. CoreSight system topology diagram - Cortex-R4 FPGA

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The Association file for this is:

Name=ARMCS-DP;Type=ARMCS-DP;Name=Cortex-R4;Type=Cortex-R4;ETM=ETMR4;Name=ETMR4;Type=CSETM;TraceOutput0=TPIU;TraceOutput1=ETB;Core=Cortex-R4;Name=ETB;Type=CSETB;Port0=ETMR4;Name=TPIU;Type=CSTPIU;Port0=ETMR4;

In this Association file:

Name=ARMCS-DP;Type=ARMCS-DP;

This line specifies the first device in our list is the ARM CoreSight Debug port. Any CoreSight components that are connected using the Debug Port associated with this template must follow this device.

Name=Cortex-R4;Type=Cortex-R4;ETM=ETMR4;

This line specifies that a Cortex-R4 processor is connected using the preceding ARMCS-DP. The ETM=ETMR4 section states that the processor has an associated ETM called ETMR4.

Name=ETMR4;Type=CSETM;TraceOutput0=TPIU;TraceOutput1=ETB;Core=Cortex-R4;

This line specifies that an ETM is accessible using the preceding ARMCS-DP.

TraceOutput0=TPIU signifies that this ETM can output into the component named Trace Port Interface Unit (TPIU).

TraceOutput1=ETB signifies that this ETM can output into the component named ETB.

Core=Cortex-R4 signifies that the source for trace captured by this ETM is the Cortex-R4 device.

Name=ETB;Type=CSETB;Port0=ETMR4;

This line specifies that a CoreSight ETB is accessible using the preceding ARMCS-DP.

Port0=ETMR4; indicates that the source of trace that is stored in this ETB is the component named ETMR4.

Name=TPIU;Type=CSTPIU;Port0=ETMR4;

This line specifies that a CoreSight TPIU is accessible using the preceding ARMCS_DP.

Port0=ETMR4; indicates that the source of trace that is routed through this TPIU is the component named ETMR4.

The following figure shows the Cortex-R4 FPGA Associations:

Figure 47. Cortex-R4 FPGA Associations

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