CoreSight device names and classes

The following table shows the name and class of all CoreSight devices that are supported by the debug hardware:

Table 3. CoreSight device names and classes

Device nameDescriptionDevice class
ARMCS-DPARM CoreSight debug port (supports both JTAG-DP and SW-DP)Debug port
CSETBCoreSight Embedded Trace Buffer (ETB)Trace sink
CSETMCoreSight Embedded Trace Macrocell (ETM)Trace source
CSETM11CoreSight Embedded Trace Macrocell designed for ARM11 (ETM11)Trace source
CSTFUNNELCoreSight Trace FunnelLink
CSTPIUCoreSight Trace Port Interface UnitTrace sink
CSHTM32CoreSight AHB Trace Macrocell (HTM32)Trace source
CSHTM64CoreSight AHB Trace Macrocell (HTM64)Trace source
CSITMCoreSight Instrumentation Trace Macrocell (ITM)Trace source
CSPTMCoreSight Program Trace Macrocell (ITM)Trace source
CSSWOCoreSight Serial Wire Output (SWO)Trace sink
ARM1136JFS-JTAG-APARM1136JF-S processor connected using JTAG-APCore
ARM1156T2FS-JTAG-APARM1156T2FS processor connected using JTAG-APCore
ARM1176JZF-JTAG-APARM1156T2FS processor connected using JTAG-APCore
Cortex-M0Cortex-M0 processorCore
Cortex-M1Cortex-M1 processorCore
Cortex-M3Cortex-M3 processorCore
Cortex-R4Cortex-R4 processorCore
Cortex-A5Cortex-A5 processorCore
Cortex-A8Cortex-A8 processorCore
Cortex-A9Cortex-A9 processorCore

The device names are the names used in debug hardware configurations and trace association files.

Show/hideSee also

Copyright © 2010-2012 ARM. All rights reserved.ARM DUI 0498G
Non-ConfidentialID071612