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Home > Designing the Target Board for Tracing with ARM DSTREAM > Probe modeling |

For trace bit rates of 0-600Mbps, basic signal integrity can be established using simplified modeling. The bulk of the transmission line model consists of the cable being used between the probe and target.

The Mictor cable is made using micro-coax and can be modeled as a 50Ω transmission line with a 1.5ns propagation delay and 0.6Ω DC resistance. The connectors at either end can be modeled as a 0.3pF capacitance to ground.

The CoreSight/MIPI cables are made using 0.635mm pitch ribbon and can be modeled as a 66Ω transmission line with a 1.5ns propagation delay and 0.4Ω DC resistance. The connectors at either end can be modeled as a 0.5pF capacitance to ground.

The JTAG 20 and JTAG 14 cables are made using 1.27mm pitch ribbon and can be modeled as a 100Ω transmission line with a 1.5ns propagation delay and 0.1Ω DC resistance. The connectors at either end can be modeled as a 1.0pF capacitance to ground.

The circuit at the probe end of the transmission line can be modeled using the following primitives:

All resistors can be modeled as their ideal resistance values with minimum/zero parasitics.

All capacitors can be modeled as their ideal capacitance values with minimum/zero parasitics.

Input comparators can be modeled using the Spartan 3 SSTLx_I model. The switching threshold can be assumed to be half of the VTref voltage as supplied by the target and data can be assumed to be valid when it is 100mV above or below this threshold.

Output drivers can be modeled using the Spartan 3 LVCMOS Fast 16mA model. The model voltage must be chosen to match the target system voltage.

All other parasitics and traces within the probe are negligible for most practical purposes.

You are strongly advised to use series termination on all target outputs to achieve good signal integrity.