Signal requirements

The data setup and hold requirements and switching thresholds for ARM DSTREAM™ are:

Show/hideData setup and hold

The following figure and table show the setup and hold timing of the trace signals with respect to TRACECLK.

Figure 31. Data waveforms

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Table 20. Data setup and hold

Tsh (min)0.75nsData setup high
Thh (min)0.75nsData hold high
Tsl (min)0.75nsData setup low
Thl (min)0.75nsData hold low


DSTREAM supports DDR clocking mode. Data is output on each edge of the TRACECLK signal and TRACECLK (max) <= 300MHz.

Show/hideSwitching Thresholds

The DSTREAM probe senses the target signaling reference voltage (VTref) and automatically adjusts its switching thresholds to VTref/2. For example, on a 3.3 volt target system, the switching thresholds are set to 1.65 volts.

Show/hideSee also

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