ARM JTAG 20 interface signals

The following table describes the signals on the ARM JTAG 20 interfaces:

Table 7. ARM JTAG 20 signals

SignalI/ODescription
TDIOutputThe Test Data In pin provides serial data to the target during debugging. TDI can be pulled HIGH on the target.
TDOInputThe Test Data Out pin receives serial data from the target during debugging. You are advised to series terminate TDO close to the target processor. TDO is typically pulled HIGH on the target.
TMSOutputThe Test Mode Select pin sets the state of the Test Access Port (TAP) controller on the target. TMS can be pulled HIGH on the target to keep the TAP controller inactive when not in use.
TCKOutputThe Test Clock pin clocks data into the TDI and TMS inputs of the target. TCK is typically pulled HIGH on the target.
RTCKInputThe Return Test Clock pin echos the test clock signal back to DSTREAM for use with adaptive mode clocking. If RTCK is generated by the target processor, you are advised to series terminate it. RTCK can be pulled HIGH or LOW on the target when not in use.
nTRSTOutputThe Test Reset pin resets the TAP controller of the processor to allow debugging to take place. nTRST is typically pulled HIGH on the target and pulled strong-LOW by DSTREAM to initiate a reset. The polarity and strength of nTRST is configurable.
nSRSTInput/OutputThe System Reset pin fully resets the target. This signal can be initiated by DSTREAM or by the target board (which is then detected by DSTREAM). nSRST is typically pulled HIGH on the target and pulled strong-LOW to initiate a reset. The polarity and strength of nSRST is configurable.
DBGRQOutputThe Debug Request pin stops the target processor and puts it into debug state. DBGRQ is rarely used by current systems and is usually pulled LOW on the target.
DBGACKInputThe Debug Acknowledge pin notifies DSTREAM that a debug request has been received and the target processor is now in debug state. DBGACK is rarely used by current systems and is usually pulled LOW on the target.
SWDIO (SWD mode)Input/OutputThe Serial Wire Data I/O pin sends and receives serial data to and from the target during debugging. You are advised to series terminate SWDIO close to the target processor.
SWCLK(SWD mode)OutputThe Serial Wire Clock pin clocks data into and out of the target during debugging.
SWO (SWD mode)InputThe Serial Wire Output pin provides trace data to DSTREAM. You are advised to series terminate SWO close to the target processor.
VTREFInputThe Voltage Target Reference pin supplies DSTREAM with the debug rail voltage of the target to match its I/O logic levels. VTREF can be tied HIGH on the target. If VTREF is pulled HIGH by a resistor, its value must be no greater than 100Ω.
GND-Ground.

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