ARM® DS-5 ARM DSTREAM System and Interface Design Reference Guide

Version 5

Table of Contents

About this book
Using this book
Typographic conventions
Other information
1 ARM DSTREAM System Design Guidelines
1.1 About adaptive clocking to synchronize the JTAG port
1.2 Reset signals
1.2.1 ARM reset signals
1.2.2 DSTREAM reset signals
1.2.3 Example reset circuits
1.3 ASIC guidelines
1.3.1 ICs containing multiple devices
1.3.2 Boundary scan test vectors
1.4 PCB guidelines
1.4.1 PCB connections
1.4.2 Target interface logic levels
2 ARM DSTREAM Target Interface Connections
2.1 Signal descriptions
2.1.1 JTAG port timing characteristics
2.1.2 Serial Wire Debug
2.1.3 About trace signals
2.2 Target connectors supported by DSTREAM
2.3 The Mictor 38 connector pinouts and interface signals
2.3.1 About the Mictor 38 connector
2.3.2 Mictor 38 pinouts
2.3.3 Mictor 38 interface signals
2.4 The ARM JTAG 20 connector pinouts and interface signals
2.4.1 About the ARM JTAG 20 connector
2.4.2 ARM JTAG 20 pinouts
2.4.3 ARM JTAG 20 interface signals
2.5 The TI JTAG 14 connector pinouts and interface signals
2.5.1 About the TI JTAG 14 connector
2.5.2 TI JTAG 14 pinouts
2.5.3 TI JTAG 14 interface signals
2.6 The ARM JTAG 14 connector pinouts and interface signals
2.6.1 About the ARM JTAG 14 connector
2.6.2 ARM JTAG 14 pinouts
2.6.3 ARM JTAG 14 interface signals
2.7 The CoreSight 10 connector pinouts and interface signals
2.7.1 About the CoreSight 10 connector
2.7.2 CoreSight 10 pinouts
2.7.3 CoreSight 10 interface signals
2.8 The CoreSight 20 connector pinouts and interface signals
2.8.1 About the CoreSight 20 connector
2.8.2 CoreSight 20 pinouts
2.8.3 CoreSight 20 interface signals
2.9 The MIPI 34 connector pinouts and interface signals
2.9.1 About the MIPI 34 connector
2.9.2 MIPI 34 pinouts
2.9.3 MIPI 34 interface signals
2.10 I/O diagrams for the DSTREAM probe connectors
2.11 Voltage domains of the DSTREAM probe
2.12 Series termination
3 ARM DSTREAM User I/O Connections
3.1 About the User I/O connector
3.2 User I/O pin connections
4 Target Board Design for Tracing with ARM DSTREAM
4.1 Overview of high-speed design
4.2 PCB track impedance
4.3 Signal requirements
4.4 Probe modeling

List of Figures

1-1 Basic JTAG port synchronizer
1-2 Timing diagram for the Basic JTAG synchronizer
1-3 JTAG port synchronizer for single rising-edge D-type ASIC design rules
1-4 Timing diagram for the D-type JTAG synchronizer
1-5 Example reset circuit logic
1-6 TAP Controllers serially chained within an ASIC
1-7 Typical PCB connections
1-8 Target interface logic levels
2-1 JTAG port timing diagram
2-2 Typical SWD connections
2-3 SWD timing diagrams
2-4 Clock waveforms
2-5 Mictor 38 connector pinout
2-6 ARM JTAG 20 connector pinout
2-7 TI JTAG 14 connector pinout
2-8 ARM JTAG 14 connector pinout
2-9 CoreSight 10 connector pinout
2-10 CoreSight 20 connector pinout
2-11 MIPI 34 connector pinout
2-12 Input
2-13 Output
2-14 Input/Output
2-15 Reset output
2-16 Reset output with feedback
2-17 VTRef input
2-18 VTRef input (decoupled)
2-19 Ground
2-20 AC Ground
3-1 User I/O pin connections
4-1 Track impedance
4-2 Data waveforms

List of Tables

2-1 DSTREAM JTAG Characteristics
2-2 SWD timing requirements
2-3 TRACECLK frequencies
2-4 Mictor 38 interface pinout table
2-5 Mictor 38 signals
2-6 ARM JTAG 20 interface pinout table
2-7 ARM JTAG 20 signals
2-8 TI JTAG 14 interface pinout table
2-9 TI JTAG 14 signals
2-10 ARM JTAG 14 interface pinout table
2-11 ARM JTAG 14 signals
2-12 CoreSight 10 interface pinout table
2-13 CoreSight 10 signals
2-14 CoreSight 20 interface pinout table
2-15 CoreSight 20 signals
2-16 MIPI 34 interface pinout table
2-17 MIPI 34 signals
2-18 Typical series terminating resistor values
3-1 User I/O pin connections
4-1 Data setup and hold

Release Information

Document History
Issue Date Confidentiality Change
A May 2010 Non-Confidential First release
B November 2010 Non-Confidential Update for DS-5 version 5.3
C 30 April 2011 Non-Confidential Update for DSTREAM and RVI v4.2.1
D 29 July 2011 Non-Confidential Update for DS-5 version 5.6
E 30 September 2011 Non-Confidential Update for DSTREAM and RVI v4.4, and DS-5 version 5.7
F 29 February 2012 Non-Confidential Update for DS-5 version 5.9
G 29 July 2012 Non-Confidential Update for DS-5 version 5.11
H 12 October 2012 Non-Confidential Update for DS-5 version 5.12
I 20 March 2015 Non-Confidential Update for DS-5 version 5.21
J 15 July 2015 Non-Confidential Update for DS-5 version 5.22
K 15 March 2016 Non-Confidential Update for DS-5 version 5.24

Non-Confidential Proprietary Notice

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Confidentiality Status

This document is Non-Confidential. The right to use, copy and disclose this document may be subject to license restrictions in accordance with the terms of the agreement entered into by ARM and the party that ARM delivered this document to.
Unrestricted Access is an ARM internal classification.

Product Status

The information in this document is Final, that is for a developed product.

Web Address

Conformance Notices

This section contains conformance notices.

Federal Communications Commission Notice

This device is test equipment and consequently is exempt from part 15 of the FCC Rules under section 15.103 (c).

Class A

Important: This is a Class A device. In residential areas, this device may cause radio interference. The user should take the necessary precautions, if appropriate.

CE Declaration of Conformity

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The system should be powered down when not in use.
It is recommended that ESD precautions be taken when handling DSTREAM, RVI, and RVT equipment.
The DSTREAM, RVI, and RVT modules generate, use, and can radiate radio frequency energy and may cause harmful interference to radio communications. There is no guarantee that interference will not occur in a particular installation. If this equipment causes harmful interference to radio or television reception, which can be determined by turning the equipment off or on, you are encouraged to try to correct the interference by one or more of the following measures:
  • ensure attached cables do not lie across the target board
  • reorient the receiving antenna
  • increase the distance between the equipment and the receiver
  • connect the equipment into an outlet on a circuit different from that to which the receiver is connected
  • consult the dealer or an experienced radio/TV technician for help


It is recommended that wherever possible shielded interface cables be used.
Non-ConfidentialPDF file icon PDF versionARM DUI0499K
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