SWD timing requirements

The functionality supports a Serial Wire Debug (SWD) connection to the Debug Access Port (DAP). SWD is an alternative protocol to JTAG for connecting to CoreSight processors, and has the advantage of requiring fewer pins than previous probes. It also supports higher data rates.

RealView® ICE connects to the serial wire-enabled target using the Low Voltage Differential Signaling (LVDS) probe. The interface uses only two lines, but for clarity the diagrams shown in the following figure separate the SWDIO line to show when it is driven by either the RealView ICE probe or target.

Figure 21. SWD timing diagrams

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The probe outputs data to SWDIO on the falling edge of SWDCLK. The probe captures data from SWDIO on the rising edge of SWDCLK. The target outputs data to SWDIO on the rising edge of SWDCLK. The target captures data from SWDIO on the rising edge of SWDCLK.

The following table shows the timing requirements for the SWD.

Table 9. SWD timing requirements

ParameterMinMaxDescription
Thigh10ns500μsSWDCLK HIGH period
Tlow10ns500μsSWDCLK LOW period
Tos-5ns5nsSWDIO Output skew to falling edge SWDCLK
Tis4ns-Input Setup time required between SWDIO and rising edge SWDCLK
Tih1ns-Input Hold time required between SWDIO and rising edge SWDCLK

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