JTAG interface signals

The following table describes the signals on the JTAG interfaces:

Table 1. JTAG signals

Signal

I/O

Description

DBGACK

-

This pin is connected in the RealView® ICE run control unit, but is not supported in the current release of the software. It is reserved for compatibility with other equipment to be used as a debug acknowledge signal from the target system. It is recommended that this signal is pulled LOW on the target.

DBGRQ

-

This pin is connected in the RealView ICE run control unit, but is not supported in the current release of the software. It is reserved for compatibility with other equipment to be used as a debug request signal to the target system. The RealView ICE software maintains this signal as LOW.

When applicable, RealView ICE uses the scan chain 2 of the processor to put the processor in debug state. It is recommended that this signal is pulled LOW on the target.

GND

-

Ground.

nSRST

Input/output

Active Low output from RealView ICE to the target system reset, with a 4.7kΩ pull-up resistor for de-asserted state. This is also an input to RealView ICE so that a reset initiated on the target can be reported to the debugger.

This pin must be pulled HIGH on the target to avoid unintentional resets when there is no connection.

nTRST

Output

Active Low output from RealView ICE to the Reset signal on the target JTAG port, driven to the VTref voltage for de-asserted state. This pin must be pulled HIGH on the target to avoid unintentional resets when there is no connection.

RTCK

Input

Return Test Clock signal from the target JTAG port to RealView ICE. Some targets must synchronize the JTAG inputs to internal clocks. To assist in meeting this requirement, you can use a returned, and retimed, TCK to dynamically control the TCK rate. RealView ICE provides Adaptive Clock Timing, that waits for TCK changes to be echoed correctly before making more changes. Targets that do not have to process TCK can ground this pin.

RTCK is not supported in Serial Wire Debug (SWD) mode.

TCK

Output

Test Clock signal from RealView ICE to the target JTAG port. It is recommended that this pin is pulled LOW on the target.

TDI

Output

Test Data In signal from RealView ICE to the target JTAG port. It is recommended that this pin is pulled HIGH on the target.

TDO

Input

Test Data Out from the target JTAG port to RealView ICE. It is recommended that this pin is pulled HIGH on the target.

TMS

Output

Test Mode signal from RealView ICE to the target JTAG port. This pin must be pulled HIGH on the target so that the effect of any spurious TCKs when there is no connection is benign.

Vsupply

Input

This pin is not connected in the RealView ICE unit. It is reserved for compatibility with other equipment to be used as a power feed from the target system.

VTref

Input

This is the target reference voltage. It indicates that the target has power, and It must be at least 0.628V. VTref is normally fed from Vdd on the target hardware and might have a series resistor (though this is not recommended). There is a 10kΩ pull-down resistor on VTref in RealView ICE.


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VTref is used to create the logic-level reference for the input comparators on TDO, RTCK and nSRST. RealView ICE clips the logic-level reference to 3.3V. RealView ICE inputs (TDO, RTCK and nSRST) are taken to high-impedance inputs of comparators. Each input is read as a logic 1 when it exceeds half the voltage reference.

VTref also controls the output logic levels to the target. RealView ICE uses analog switches to drive the output signals. The output is connected to ground for a logic 0 and to the JTAG interface voltage for a logic 1.

TDI, TMS and TCK have 47Ω series resistors on the Low Voltage Differential Signaling (LVDS) probe. All other outputs from the LVDS probe and the RealView ICE 20-way connector have 100Ω series resistors.

nSRST and nTRST are both active low signals. When asserted, both these signals are connected to ground for a logic 0. When de-asserted, nSRST uses a 4.7kΩ pull-up for a logic 1, whereas nTRST is driven to the VTref voltage for de-asserted state.

You must ensure that your board has appropriate pull-up and pull-down resistors on the JTAG signals:

  • TMS, TDI, TDO, nSRST and nTRST must have pull-ups.

  • TCK must have a pull-down to enable hot swap and post-mortem debugging

  • RTCK must have a pull-down to fix a stable value on that signal when debugging a non-synthesizable processor.

  • DBGRQ must have a pull-down. This ensures that the processor does not enter debug state in an uncontrolled way.

  • DBGACK must have a pull-down, so the default value that the debugger sees is processor not in debug state.

The recommended value for pull-ups and pull-downs is 10kΩ, although the optimum value depends on the signal load. For example, pull-downs must be about 1kΩ when working with TTL logic.

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