Target interface

The functionality available for use with the Low Voltage Differential Signaling (LVDS) probe supports a Serial Wire Debug (SWD) connection to the Debug Access Port (DAP). SWD is an alternative protocol to JTAG for connecting to CoreSight processors, and has the advantage of requiring fewer pins than previous probes. It also supports higher data rates.

The following table shows the SWD pinout for the connector alongside the JTAG pinout.

Table 8. SWD interface pinout

PinSignalPinSignal
JTAGSerial Wire
1VTrefVTref2NC
3nTRSTNC4GND
5TDINC6GND
7TMSSWDIO8GND
9TCKSWDCLK10GND
11RTCKNC12GND
13TDOSWO14GND
15nSRSTnSRST16GND
17DBGRQDBGRQ18GND
19DBGACKDBGACK20GND

Show/hideSee also

Copyright © 2010-2011 ARM. All rights reserved.ARM DUI 0517D
Non-ConfidentialID071311