2.3. Parameters

Configure the tarmac trace plug-in using the parameters listed in Table 2.1. The parameters appear prefixed with the path TRACE.instancename, where instance-name is TarmacTrace unless overridden. See Starting the simulation.

Table 2.1. Parameter descriptions

Parameter name

Type

Default Value

Description

trace-file

String

Empty

Name of the trace output file. If empty (default) the trace output is printed on stdout.

trace-file-per-comp

Boolean

False

Create a separate trace file for each component traced. At present the only components that support trace are cores, so this option is only relevant when there are multiple cores. The component name is added to the trace file name to disambiguate it.

trace-inst-stem

String

Empty

If set to a component path only a sub tree of components is traced. In the simplest case this can be set to the component path of a single CPU then only this CPU is traced.

trace_instructions

Boolean

True

Determines whether instructions should be traced.

trace_core_registers

Boolean

True

Determines whether core registers (R0-R14, CPSR and SPSR) should be traced. This produces a lot of data and can considerably slow down simulation.

trace_vfp

Boolean

True

Determines whether VFP and NEON registers (including FPSCR and FPEXC) should be traced.

trace_cp15

Boolean

True

Determines whether writes to CP15 registers should be traced.

VMSA

Boolean

True

Determines whether the core implements the ‘Virtual Memory Storage Architecture’ (=True) or ‘Protected Memory Storage Architecture’ (=false). For cores with an MMU (for example Cortex A8 and Cortex A9) set this to True. On Cores with an MPU (for example Cortex R4) set this to False. This influences how CP15 registers are traced.

trace_branches

Boolean

False

Trace all non-sequential changes of the program flow. The information traced is sufficient to completely reconstruct program flow, and the tracing is fairly efficient.

trace_bus_accesses

Boolean

False

Trace all bus accesses. This forces all direct memory accesses to turn into full transaction which considerably slows down the simulation.

trace_loads_stores

Boolean

True

Determines whether load/stores are traced. This is much cheaper performance-wise than bus tracing.

trace_events

Boolean

True

Determines whether exceptions and mode changes (for cores implementing modes) are traced.

start-instruction-count

Integer

0x0Set the instruction count where tracing starts. Default 0x0 is to start from the beginning.
end-instruction-count

Integer

0x0Set the instruction count where tracing ends. Default 0x0 is to trace until the end of the simulation.
loadstore-display-width

Integer

0x4Memory transactions can in the case of LDM/STM involve up to 64 bytes. For easier readability you can break these up into multiple memory access records with a smaller size of bytes. 0 means not to break up any transaction. The default 4 means to break up transactions into words.

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