3.6. Memory bus trace

If enabled, transactions initiated through the memory bus master port of the core are traced.

These accesses use physical addresses, and are traced in the following command syntax:

<time> <scale> B<rw><sz><fd><lk><p><s> l<wrcbs> O<wrcbs> <master_id> <addr> <data>

The fields have the following meaning:

<time>

Timestamp (decimal value).

<scale>

Unit for the previous field <time>. This is used for consistency with device-specific tarmac trace formats.

<rw>

R indicates a read access, and W indicates a write access.

<sz>

Size of the data transfer in bytes.

<fd>

I indicates an opcode fetch, D indicates a data load/store or an MMU access.

<lk>

L indicates a locked access, X indicates an exclusive access, an underscore “_” indicates a normal access.

<p>

P indicates a privileged access, an underscore “_” indicates a normal access.

<s>

S indicates a secure access, N indicates a non-secure access.

I<wrcbs>

The inner cache attributes. See O<wrcbs> .

O<wrcbs>

The outer cache attributes:

<w>

W indicates allocate on write. An underscore “_” indicates no allocate on write

<r>

R indicates allocate on read. An underscore “_” indicates no allocate on read

<c>

C indicates a cacheable access. An underscore “_” indicates a non-cacheable access

<b>

B indicates a bufferable access. An underscore “_” indicates a non-bufferable access

<s>

S indicates a shareability access. An underscore “_” indicates a non-shareability access.

<master_id>

The master ID of the transaction.

<addr>

Physical address used to access memory in hexadecimal format.

<data>

Hexadecimal value of data transferred. The value is padded according to the size of the transfer. Bytes are ordered from lowest to highest byte. This means that for accesses in little endian mode, the data occurs mirrored compared to the register/memory access records.

Note

This event is not shown in the trace example file.

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