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If enabled, all writes to the processor registers are traced. This includes writes to core registers R0 to R14, CPSR and SPSR, VFP registers such as S0 to S31, D0 to D31, FPSCR, FPEXC, and writes to CP14 and CP15 registers. Banked registers are traced separately using the mode as a suffix to the register name, for example r13 (current register R13) and r13_mon (banked register R13).
Register traces have the following command syntax:
<time> <scale> R <register> <value>
The fields have the following meanings:
Timestamp (decimal value).
Unit for the previous field
This is used for consistency with device-specific tarmac trace formats.
Register name in lowercase letters. Banked core
registers can have a mode appended with a single underscore. Banked
CP14/CP15 registers have
to indicate access of either the secure or non-secure banked register.
Hexadecimal value written to the register (64 bits maximum).