CoreTile Express A5x2 Technical Reference ManualCortex™-A5 MPCore (V2P-CA5s)
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2.1. Overview of the CoreTile Express A5x2 daughterboard

Figure 2.1 shows a block diagram of the daughterboard.

Figure 2.1. CoreTile Express A5x2 daughterboard block diagram

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The daughterboard contains the following devices and interfaces:

Cortex-A5 MPCore test chip

The test chip includes the following components and interfaces:

  • Cortex-A5 MPCore cluster.

  • L2C-310 Level 2 Cache Controller (L2CC) consisting of 256KB of L2 unified cache.

  • PL341 64-bit Double Data Rate 2 (DDR2) Dynamic Memory Controller (DMC) interface to the onboard 1GB DDR2 SO-DIMM.

  • PL354 32-bit Static Memory Bus (SMB) controller, SMC.

  • 24-bit Color HDLCD (CLCD) controller.

  • Multiplexed 64-bit AXI master interface.

  • Multiplexed 64-bit AXI slave interface.

  • CoreSight debug and trace interface to the onboard connectors.

  • Daughterboard Configuration Controller interface.

Daughterboard Configuration Controller

The Daughterboard Configuration Controller initiates, controls, and configures the test chip. It interfaces with the Motherboard Express µATX.

A Motherboard Configuration Controller (MCC) on the Motherboard Express µATX configures the daughterboard and communicates with the Daughterboard Configuration Controller to configure the test chip.

Configuration EEPROM

The daughterboard EEPROM contains information for identification and detection of the daughterboard and stores the filename of the SPI flash image and its file creation date.

DDR2 SO-DIMM

The daughterboard supports 1GB of 64-bit DDR2 SO-DIMM memory.

Clock generator logic

The daughterboard provides six on-board OSCCLKS to drive the CPU and internal AXI, AXIM, DDR2, SMC, and HDLCD interfaces.

CoreSight software debug and trace ports

The Cortex-A5 MPCore test chip CoreSight system supports both the SWD and JTAG protocols.

A 32-bit trace interface is provided through the standard dual 16-bit Matched Impedance ConnecTOR (MICTOR) connectors.

System interconnect buses

See System interconnect signals.

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