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2.10. DDR2 SO-DIMM memory interface

The Cortex-A5 DDR2 SO-DIMM memory interface uses a PL341 Dynamic Memory Controller (DMC). The DMC runs asynchronously to the AXI matrix so the AXI sub-system does not impose frequency limitations on the DMC interface.

Figure 2.15 shows a functional overview of the DDR2 SO-DIMM memory interface.

Figure 2.15. DDR2 SO-DIMM memory interface

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Note

  • OSCCLK2 is the source for DDRCLK90, nDDRCLK, and DDRCLK.

    OSCCLK0 is the source for AXICLK.

    See Figure 2.9 and Table 2.2.

  • ARM recommends that you use the SO-DIMM memory supplied with the CoreTile Express A5x2 daughterboard. ARM does not recommend using alternative DIMMs.

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