CoreTile Express A5x2 Technical Reference Manual: 2.6.2. Test chip interrupts

2.6.2. Test chip interrupts

Table 2.4 shows the interrupts from the motherboard IOFPGA, the interrupts from the test chip peripherals, the interrupts from the MPCore cluster and the reserved interrupts.

Table 2.4. Test chip interrupts

GIC interrupt	SB_IRQ[] interrupt from the motherboard	Source	Signal	Description
0:31	Not applicable	MPCore cluster	-	Private peripheral connections between CPUs and GIC
32	0	IOFPGA	WDOG0INT	Watchdog timer
33	1	IOFPGA	SWINT	Software interrupt
34	2	IOFPGA	TIM01INT	Dual Timer 0/1 interrupt
35	3	IOFPGA	TIM23INT	Dual Timer 2/3 interrupt
36	4	IOFPGA	RTCINTR	Real time clock interrupt
37	5	IOFPGA	UART0INTR	UART0 interrupt
38	6	IOFPGA	UART1INTR	UART1 interrupt
39	7	IOFPGA	UART2INTR	UART2 interrupt
40	8	IOFPGA	UART3INTR	UART3 interrupt
41	9	IOFPGA	MCI_INTR[0]	Media card interrupt
42	10	IOFPGA	MCI_INTR[1]	Media card interrupt
43	11	IOFPGA	AACI_INTR	Audio CODEC interrupt
44	12	IOFPGA	KMI0_INTR	Keyboard, mouse interrupt
45	13	IOFPGA	KMI1_INTR	Keyboard, mouse interrupt
46	14	IOFPGA	CLCDINTR	Display interrupt
47	15	IOFPGA	ETH_INTR	Ethernet interrupt
48	16	IOFPGA	USB_nINT	USB interrupt
49	17	IOFPGA	PCIE_GPEN	PCI-Express interrupt
53:50	21:18	IOFPGA	SB1_INT[3:0]	Copy of SB_IRQ[35:32]
57:54	25:22	IOFPGA	SB2_INT[3:0]	Copy of SB_IRQ[39:36]
63:58	31:26	IOFPGA	-	Tied to `b0` in IOFPGA
67:64	35:32	IOFPGA	SB1_INT[3:0]	Interrupts INT[3:0] from Site 1 daughterboard when you fit the V2P-CA5s daughterboard in site 2
71:68	39:36	IOFPGA	SB2_INT[3:0]	Interrupts INT[3:0] from Site 2 daughterboard when you fit the V2P-CA5s daughterboard in site 1
79:72	47:40	IOFPGA	-	Tied to `b0` in IOFPGA
99:80	Not applicable	`b0`	-	Reserved
100	Not applicable	Test chip	-	CPU0 performance monitor unit
101	Not applicable	Test chip	-	CPU1 performance monitor unit
102	Not applicable	Test chip	-	Reserved
103	Not applicable	Test chip	-	Reserved
104	Not applicable	Test chip	-	CPU0 cross trigger interrupt
105	Not applicable	Test chip	-	CPU1 cross trigger interrupt
106	Not applicable	Test chip	-	Reserved
107	Not applicable	Test chip	-	Reserved
108	Not applicable	Test chip	-	CPU0 CP14 DTR COMMTX Interrupt
109	Not applicable	Test chip	-	CPU1 CP14 DTR COMMTX interrupt
110	Not applicable	Test chip	-	Reserved
111	Not applicable	Test chip	-	Reserved
112	Not applicable	Test chip	-	CPU0 CP14 DTR COMMRX interrupt
113	Not applicable	Test chip	-	CPU1 CP14 DTR COMMRX interrupt
114	Not applicable	Test chip	-	Reserved
115	Not applicable	Test chip	-	Reserved
116	Not applicable	Test chip	-	L2 cache controller interrupt
117	Not applicable	Test chip	-	HDLCD interrupt
118	Not applicable	Test chip	-	SMC interface 0 interrupt
119	Not applicable	Test chip	-	SMC interface 1 interrupt
127:120	Not applicable	`b0`	-	Reserved

Note

For more information on the motherboard peripherals that generate interrupts to the test chip, see the Motherboard Express µATX Technical Reference Manual.

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