You can attach a JTAG debugger to the daughterboard JTAG connector to execute programs to the daughterboard and debug them. For convenience, connect the cable from the rear panel JTAG connector to the daughterboard JTAG. For example, you can connect the RealView Debugger to this debug interface using an external RealView ICE interface box.

See Figure 1.1 for the location of the JTAG ICE connector.

Figure 2.14 shows an overview of the CoreSight system.

For information on CoreSight components, see the CoreSight Components Technical Reference Manual.

For information on Cortex-A5 ETM, see the CoreSight ETM-A5 Technical Reference Manual.

The daughterboard supports up to 32-bit trace in continuous mode. There are two MICTOR connectors for JTAG trace. See Figure 1.1 for the location of these connectors.

To set up a trace connection to either of the cores on the test chip, you must know the funnel port number and ETM base address connection information associated with each core. Table 2.6 defines these addresses for both cores on the test chip.

See Daughterboard memory map for the memory addresses of all CoreSight components.