CoreTile Express A5x2 Technical Reference Manual: B.2.2. Register summary

B.2.2. Register summary

Table B.1 shows the registers in offset order from the base memory address. The base memory address of the HDLCD controller on the Cortex-A5 MPCore test chip is 0x2A11_0000.

Table B.1. Register summary

Offset	Name	Type	Reset	Width	Description
`0x0000`	VERSION	RO	VERSION	32	Version Register
`0x0010`	INT_RAWSTAT	RW	`0x0`	32	Interrupt Raw Status Register
`0x0014`	INT_CLEAR	WO	N/A	32	Interrupt Clear Register
`0x0018`	INT_MASK	RW	`0x0`	32	Interrupt Mask Register
`0x001C`	INT_STATUS	RO	`0x0`	32	Interrupt Status Register
`0x0100`	FB_BASE	RW	`0x0`	32	Frame Buffer Base Address Register
`0x0104`	FB_LINE_LENGTH	RW	`0x0`	32	Frame Buffer Line Length Register
`0x0108`	FB_LINE_COUNT	RW	`0x0`	32	Frame Buffer Line Count Register
`0x010C`	FB_LINE_PITCH	RW	`0x0`	32	Frame Buffer Line Pitch Register
`0x0110`	BUS_OPTIONS	RW	`0x408`	32	Bus Options Register
`0x0200`	V_SYNC	RW	`0x0`	32	Vertical Synch Width Register
`0x0204`	V_BACK_PORCH	RW	`0x0`	32	Vertical Back Porch Width Register
`0x0208`	V_DATA	RW	`0x0`	32	Vertical Data Width Register
`0x020C`	V_FRONT_PORCH	RW	`0x0`	32	Vertical Front Porch Width Register
`0x0210`	H_SYNC	RW	`0x0`	32	Horizontal Synch Width Register
`0x0214`	H_BACK_PORCH	RW	`0x0`	32	Horizontal Back Porch Width Register
`0x0218`	H_DATA	RW	`0x0`	32	Horizontal Data Width Register
`0x021C`	H_FRONT_PORCH	RW	`0x0`	32	Horizontal Front Porch Width Register
`0x0220`	POLARITIES	RW	`0x0`	32	Polarities Register
`0x0230`	COMMAND	RW	`0x0`	32	Command Register
`0x0240`	PIXEL_FORMAT	RW	`0x0`	32	Pixel Format Register
`0x0244`	RED_SELECT	RW	`0x0`	32	Color Select Registers
`0x0248`	GREEN_SELECT	RW	`0x0`	32	Color Select Registers
`0x024C`	BLUE_SELECT	RW	`0x0`	32	Color Select Registers

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