CoreTile Express™ A5x2 Technical Reference Manual

Cortex™-A5 MPCore (V2P-CA5s)


Table of Contents

Preface
About this book
Intended audience
Using this book
Glossary
Conventions
Additional reading
Feedback
Feedback on this product
Feedback on content
1. Introduction
1.1. About the CoreTile Express A5x2 daughterboard
1.2. Precautions
1.2.1. Ensuring safety
1.2.2. Preventing damage
2. Hardware Description
2.1. Overview of the CoreTile Express A5x2 daughterboard
2.2. Cortex-A5 MPCore test chip
2.3. System interconnect signals
2.3.1. High-Speed Buses (HSBs) to other daughterboard
2.3.2. Static Memory Bus (SMB)
2.3.3. MultiMedia Bus (MMB)
2.3.4. System Bus (SB)
2.3.5. Configuration Bus (CB)
2.4. Power-up configuration and resets
2.4.1. Configuration architecture
2.4.2. System configuration
2.4.3. Resets
2.4.4. Configuration and reset signals
2.5. Clocks
2.5.1. Overview of clocks
2.5.2. Programmable clock generators
2.5.3. External clocks
2.6. Interrupts
2.6.1. Overview of interrupts
2.6.2. Test chip interrupts
2.7. Serial configuration controller
2.8. Temperature monitoring
2.9. Debug
2.10. DDR2 SO-DIMM memory interface
2.11. HDLCD
3. Programmers Model
3.1. About this programmers model
3.2. Daughterboard memory map
3.2.1. Remapping memory
3.2.2. Overview of the memory map for the on-chip peripherals
3.3. Programmable peripherals and interfaces
3.3.1. Cortex-A5 MPCore cluster
3.3.2. AMBA network interconnect, NIC-301
3.3.3. HDLCD controller
3.3.4. L2 cache controller, L2C-310
3.3.5. PrimeCell DDR2 DMC interface, PL341
3.3.6. PrimeCell SMC dual SRAM memory interface, PL354
3.3.7. Test chip SCC registers
A. Signal Descriptions
A.1. Daughterboard connectors
A.2. HDRX HSB multiplexing scheme
A.3. Header Connectors
A.4. Debug and trace connectors
A.4.1. JTAG connector
A.4.2. Trace connectors
A.5. SO-DIMM connector
B. HDLCD controller
B.1. About the HDLCD controller
B.2. HDLCD programmers model
B.2.1. About the HDLCD controller programmers model
B.2.2. Register summary
B.2.3. Register descriptions
C. Electrical Specifications
C.1. AC characteristics
D. Revisions

List of Figures

1. Key to timing diagram conventions
1.1. CoreTile Express A5x2 daughterboard layout
2.1. CoreTile Express A5x2 daughterboard block diagram
2.2. Top-level view of the Cortex-A5 MPCore test chip components
2.3. System connect example with optional LogicTile Express 3MG daughterboard
2.4. CoreTile Express A5x2 configuration architecture with Motherboard Express, V2M-P1
2.5. CoreTile Express A5x2 configuration architecture with custom motherboard
2.6. CoreTile Express A5x2 daughterboard resets
2.7. CoreTile Express A5x2 daughterboard configuration and reset timing cycle
2.8. System clocks overview
2.9. CoreTile Express A5x2 daughterboard clocks
2.10. CoreTile Express A5x2 daughterboard interrupt overview
2.11. Overview of SCC connectivity
2.12. Daughterboard Configuration Controller read from SCC
2.13. Daughterboard Configuration Controller write to SCC
2.14. CoreTile Express A5x2 CoreSight and Trace
2.15. DDR2 SO-DIMM memory interface
2.16. HDLCD graphics system interconnect
3.1. CoreTile Express A5x2 daughterboard memory map
3.2. Cortex-A5 MPCore on-chip peripheral memory map
3.3. Test chip CFGRW0 Register bit assignments
3.4. Test chip CFGRW1 Register bit assignments
3.5. Test chip CFGRW2 Register bit assignments
3.6. Test chip CFGRW3 Register bit assignments
3.7. Test chip CFGRW4 Register bit assignments
3.8. Test chip CFGRW5 Register bit assignments
3.9. Test chip CFGRW6 Register bit assignments
3.10. Test chip CFGRW7 Register bit assignments
3.11. Test chip APBCLEAR Register bit assignments
3.12. Test chip DEVICEID Register bit assignments
3.13. Test chip CPUID Register bit assignments
A.1. CoreTile Express A5x2 daughterboard connectors
A.2. HSB multiplexing
A.3. JTAG connector, J5
A.4. Trace Connector, J6 and J7
B.1. Version Register bit assignments
B.2. Interrupt Raw Status Register bit assignments
B.3. Interrupt Clear Register bit assignments
B.4. Interrupt Mask Register bit assignments
B.5. Interrupt Status Register bit assignments
B.6. Frame Buffer Base Address Register bit assignments
B.7. Frame Buffer Line Length Register bit assignments
B.8. Frame Buffer Line Count Register bit assignments
B.9. Frame Buffer Line Count Pitch bit assignments
B.10. Bus Options Register bit assignments
B.11. Vertical Synch Width Register bit assignments
B.12. Vertical Back Porch Width Register bit assignments
B.13. Vertical Data Width Register bit assignments
B.14. Vertical Front Porch Width Register bit assignments
B.15. Horizontal Synch Width Register bit assignments
B.16. Horizontal Back Porch Width Register bit assignments
B.17. Horizontal Data Width Register bit assignments
B.18. Horizontal Front Porch Width Register bit assignments
B.19. Polarities Register bit assignments
B.20. Command Register bit assignments
B.21. Little endian byte layout
B.22. Big endian byte layout
B.23. Pixel Format Register bit assignments
B.24. Color Select Register bit assignments

List of Tables

1.
2.1. Configuration and reset signals
2.2. Daughterboard OSCCLK clock sources
2.3. External clock sources
2.4. Test chip interrupts
2.5. Device number Daughterboard Configuration Controller temperature monitoring
2.6. Test chip Trace connection addresses
3.1. Peripheral memory map
3.2. Test chip SCC register summary
3.3. Test chip CFGRW0 Register bit assignments
3.4. Test chip CFGRW1 register bit assignments
3.5. Test chip CFGRW2 Register bit assignments
3.6. Test chip CFGRW3 Register bit assignments
3.7. Test chip CFGRW4 Register bit assignments
3.8. Test chip CFGRW5 Register bit assignments
3.9. Test chip CFGRW6 Register bit assignments
3.10. Test chip CFGRW7 Register bit assignments
3.11. Test chip APBCLEAR Register bit assignments
3.12. Test chip DEVICEID Register bit assignments
3.13. Test chip CPUID Register bit assignments
A.1. P-JTAG connector, J5, signal list
A.2. Trace Single connector, J6, signal list
A.3. Trace Dual connector, J7, signal list
B.1. Register summary
B.2. Version Register bit assignments
B.3. Interrupt Raw Status Register bit assignments
B.4. Interrupt Clear Register bit assignments
B.5. Interrupt Mask Register bit assignments
B.6. Interrupt Status Register bit assignments
B.7. Frame Buffer Base Address Register bit assignments
B.8. Frame Buffer Line Length Register bit assignments
B.9. Frame Buffer Line Count Register bit assignments
B.10. Frame Buffer Line Pitch Register bit assignments
B.11. Bus Options Register bit assignments
B.12. Vertical Synch Register bit assignments
B.13. Vertical Back Porch Register bit assignments
B.14. Vertical Data Width Register bit assignments
B.15. Vertical Front Porch Width Register bit assignments
B.16. Horizontal Synch Width Register bit assignments
B.17. Horizontal Back Porch Register bit assignments
B.18. Horizontal Data Width Register bit assignments
B.19. Horizontal Front Porch Register bit assignments
B.20. Polarities Register bit assignments
B.21. Command Register bit assignments
B.22. Pixel Format Register bit assignments
B.23. Color Select Register bit assignments
C.1. AC characteristics
D.1. Issue A
D.2. Differences between Issue A and Issue B
D.3. Differences between Issue B and Issue C

Proprietary Notice

Words and logos marked with ® or ™ are registered trademarks or trademarks of ARM® in the EU and other countries, except as otherwise stated below in this proprietary notice. Other brands and names mentioned herein may be the trademarks of their respective owners.

Neither the whole nor any part of the information contained in, or the product described in, this document may be adapted or reproduced in any material form except with the prior written permission of the copyright holder.

The product described in this document is subject to continuous developments and improvements. All particulars of the product and its use contained in this document are given by ARM in good faith. However, all warranties implied or expressed, including but not limited to implied warranties of merchantability, or fitness for purpose, are excluded.

This document is intended only to assist the reader in the use of the product. ARM shall not be liable for any loss or damage arising from the use of any information in this document, or any error or omission in such information, or any incorrect use of the product.

Where the term ARM is used it means “ARM or any of its subsidiaries as appropriate”.

Confidentiality Status

This document is Non-Confidential. The right to use, copy and disclose this document may be subject to license restrictions in accordance with the terms of the agreement entered into by ARM and the party that ARM delivered this document to.

Product Status

The information in this document is final, that is for a developed product.

Conformance Notices

This section contains conformance notices.

Federal Communications Commission Notice

This device is test equipment and consequently is exempt from part 15 of the FCC Rules under section 15.103 (c).

CE Declaration of Conformity

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The system should be powered down when not in use.

The daughterboard generates, uses, and can radiate radio frequency energy and may cause harmful interference to radio communications. However, there is no guarantee that interference will not occur in a particular installation. If this equipment causes harmful interference to radio or television reception, which can be determined by turning the equipment off or on, you are encouraged to try to correct the interference by one or more of the following measures:

  • Ensure attached cables do not lie across the card.

  • Reorient the receiving antenna.

  • Increase the distance between the equipment and the receiver.

  • Connect the equipment into an outlet on a circuit different from that to which the receiver is connected.

  • Consult the dealer or an experienced radio/TV technician for help.

Note

It is recommended that wherever possible shielded interface cables be used.

Revision History
Revision A28 March 2011First release
Revision B14 August 2012Second release
Revision C31 March 2013Third release
Copyright © 2011-2013 ARM. All rights reserved.DUI 0541C
Non-ConfidentialID040613