Cortex-M3 Devices Generic User Guide
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3.6.3. SDIV and UDIV

Signed Divide and Unsigned Divide.

Syntax

SDIV{cond} {Rd,} Rn, Rm

UDIV{cond} {Rd,} Rn, Rm

where:

cond

Is an optional condition code, see Conditional execution.

Rd

Specifies the destination register. If Rd is omitted, the destination register is Rn.

Rn

Specifies the register holding the value to be divided.

Rm

Is a register holding the divisor.

Operation

SDIV performs a signed integer division of the value in Rn by the value in Rm.

UDIV performs an unsigned integer division of the value in Rn by the value in Rm.

For both instructions, if the value in Rn is not divisible by the value in Rm, the result is rounded towards zero.

Restrictions

Do not use SP and do not use PC.

Condition flags

These instructions do not change the flags.

Examples

    SDIV  R0, R2, R4  ; Signed divide, R0 = R2/R4
    UDIV  R8, R8, R1  ; Unsigned divide, R8 = R8/R1.
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