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The processor core registers are:
Table 2.2. Core register set summary
| Name | Type [a] | Required privilege [b] | Reset value | Description |
|---|---|---|---|---|
| R0-R12 | RW | Either | Unknown | General-purpose registers |
| MSP | RW | Privileged | See description | Stack Pointer |
| PSP | RW | Either | Unknown | Stack Pointer |
| LR | RW | Either | 0xFFFFFFFF | Link Register |
| PC | RW | Either | See description | Program Counter |
| PSR | RW | Privileged | 0x01000000 | Program Status Register |
| ASPR | RW | Either | Unknown | Application Program Status Register |
| IPSR | RO | Privileged | 0x00000000 | Interrupt Program Status Register |
| EPSR | RO | Privileged | 0x01000000 | Execution Program Status Register |
| PRIMASK | RW | Privileged | 0x00000000 | Priority Mask Register |
| FAULTMASK | RW | Privileged | 0x00000000 | Fault Mask Register |
| BASEPRI | RW | Privileged | 0x00000000 | Base Priority Mask Register |
| CONTROL | RW | Privileged | 0x00000000 | CONTROL register |
[a] Describes access type during program execution in thread mode and Handler mode. Debug access can differ. [b] An entry of Either means privileged and unprivileged software can access the register. | ||||
The Stack Pointer (SP) is register R13. In Thread mode, bit[1] of the CONTROL register indicates the stack pointer to use:
0 = Main Stack Pointer (MSP). This is the reset value.
1 = Process Stack Pointer (PSP).
On
reset, the processor loads the MSP with the value from address 0x00000000.
The Link Register (LR) is register R14.
It stores the return information for subroutines, function calls,
and exceptions. On reset, the processor sets the LR value to 0xFFFFFFFF.
The Program Counter (PC) is register
R15. It contains the current program address. On reset, the processor
loads the PC with the value of the reset vector, which is at address 0x00000004. Bit[0]
of the value is loaded into the EPSR T-bit at reset and must be
1.
The Program Status Register (PSR) combines:
Application Program Status Register (APSR)
Interrupt Program Status Register (IPSR)
Execution Program Status Register (EPSR).
These registers are mutually exclusive bitfields in the 32-bit PSR. The bit assignments are:
Access these registers individually or as a combination of
any two or all three registers, using the register name as an argument
to the MSR or MRS instructions. For example:
read all of the registers
using PSR with the MRS instruction
write to the APSR N, Z, C, V, and Q bits using APSR_nzcvq with
the MSR instruction.
The PSR combinations and attributes are:
See the instruction descriptions MRS and MSR for more information about how to access the program status registers.
The APSR contains the current state of the condition flags from previous instruction executions. See the register summary in Table 2.2 for its attributes. The bit assignments are:
Table 2.4. APSR bit assignments
| Bits | Name | Function |
|---|---|---|
| [31] | N | Negative flag |
| [30] | Z | Zero flag |
| [29] | C | Carry or borrow flag |
| [28] | V | Overflow flag |
| [27] | Q | Saturation flag |
| [26:0] | - | Reserved |
The IPSR contains the exception type number of the current Interrupt Service Routine (ISR). See the register summary in Table 2.2 for its attributes. The bit assignments are:
Table 2.5. IPSR bit assignments
| Bits | Name | Function |
|---|---|---|
| [31:9] | - | Reserved. |
| [8:0] | ISR_NUMBER | This is the number of the current exception: 0 = Thread mode 1 = Reserved 2 = NMI 3 = HardFault 4 = MemManage 5 = BusFault 6 = UsageFault 7-10 = Reserved 11 = SVCall 12 = Reserved for Debug 13 = Reserved 14 = PendSV 15 = SysTick 16 = IRQ0 . . . n+15 = IRQ(n-1)[a]. See Exception types for more information. |
[a] The number of interrupts, n, is implementation-defined, in the range 1-240. | ||
The EPSR contains the Thumb state bit, and the execution state bits for either the:
If-Then (IT) instruction
Interruptible-Continuable Instruction (ICI) field for an interrupted load multiple or store multiple instruction.
See the register summary in Table 2.2 for the EPSR attributes. The bit assignments are:
Table 2.6. EPSR bit assignments
| Bits | Name | Function |
|---|---|---|
| [31:27] | - | Reserved. |
| [26:25], [15:10] | ICI/IT | Indicates the interrupted position of
a continuable instruction, see Interruptible-continuable instructions, or the execution state of an |
| [24] | T | Thumb state bit, see Thumb state. |
| [23:16] | - | Reserved. |
| [9:0] | - | Reserved. |
Attempts to read the EPSR directly through application software
using the MSR instruction always return zero. Attempts
to write the EPSR using the MSR instruction in application
software are ignored.
When an interrupt occurs during the execution of an LDM, STM, PUSH,
or POP instruction, the processor:
stops the load multiple or store multiple instruction operation temporarily
stores the next register operand in the multiple operation to EPSR bits[15:12].
After servicing the interrupt, the processor:
returns to the register pointed to by bits[15:12]
resumes execution of the multiple load or store instruction.
When the EPSR holds ICI execution state, bits[26:25,11:10] are zero.
The If-Then block contains up to four instructions following
an IT instruction. Each instruction in the block is
conditional. The conditions for the instructions are either all
the same, or some can be the inverse of others. See IT for more information.
The Cortex-M3 processor only supports execution of instructions in Thumb state. The following can clear the T bit to 0:
instructions BLX, BX and POP{PC}
restoration from the stacked xPSR value on an exception return
bit[0] of the vector value on an exception entry or reset.
Attempting to execute instructions when the T bit is 0 results in a fault or lockup. See Lockup for more information.
The exception mask registers disable the handling of exceptions by the processor. Disable exceptions where they might impact on timing critical tasks.
To access the exception mask registers use the MSR and MRS instructions,
or the CPS instruction to change the value of PRIMASK
or FAULTMASK. See MRS, MSR, and CPS for more information.
The PRIMASK register prevents activation of all exceptions with configurable priority. See the register summary in Table 2.2 for its attributes. The bit assignments are:
Table 2.7. PRIMASK register bit assignments
| Bits | Name | Function |
|---|---|---|
| [31:1] | - | Reserved |
| [0] | PRIMASK | 0 = no effect 1 = prevents the activation of all exceptions with configurable priority. |
The FAULTMASK register prevents activation of all exceptions except for Non-Maskable Interrupt (NMI). See the register summary in Table 2.2 for its attributes. The bit assignments are:
Table 2.8. FAULTMASK register bit assignments
| Bits | Name | Function |
|---|---|---|
| [31:1] | - | Reserved |
| [0] | FAULTMASK | 0 = no effect 1 = prevents the activation of all exceptions except for NMI. |
The processor clears the FAULTMASK bit to 0 on exit from any exception handler except the NMI handler.
The BASEPRI register defines the minimum priority for exception processing. When BASEPRI is set to a nonzero value, it prevents the activation of all exceptions with the same or lower priority level as the BASEPRI value. See the register summary in Table 2.2 for its attributes. The bit assignments are:
Table 2.9. BASEPRI register bit assignments
| Bits | Name | Function |
|---|---|---|
| [31:8] | - | Reserved |
| [7:0] | BASEPRI [a] | Priority mask bits:
Nonzero = defines the base priority for exception processing. The processor does not process any exception with a priority value greater than or equal to BASEPRI. |
[a] This field is similar to the priority fields in the interrupt priority registers. Register priority value fields are 8 bits wide, and non-implemented low-order bits read as zero and ignore writes. See Interrupt Priority Registers for more information. Higher priority field values correspond to lower exception priorities. | ||
The CONTROL register controls the stack used and the privilege level for software execution when the processor is in Thread mode. See the register summary in Table 2.2 for its attributes. The bit assignments are:
Table 2.10. CONTROL register bit assignments
| Bits | Name | Function |
|---|---|---|
| [31:2] | - | Reserved. |
| [1] | SPSEL | Defines the currently active stack pointer: In Handler mode this bit reads as zero and ignores writes. The Cortex-M3 updates this bit automatically on exception return. 0 = MSP is the current stack pointer 1 = PSP is the current stack pointer. |
| [0] | nPRIV | Defines the Thread mode privilege level: 0 = Privileged 1 = Unprivileged. |
Handler mode always uses the MSP, so the processor ignores explicit writes to the active stack pointer bit of the CONTROL register when in Handler mode. The exception entry and return mechanisms automatically update the CONTROL register based on the EXC_RETURN value, see Table 2.17.
In an OS environment, ARM recommends that threads running in Thread mode use the process stack and the kernel and exception handlers use the main stack.
By default, Thread mode uses the MSP. To switch the stack pointer used in Thread mode to the PSP, either:
use the MSR instruction to set the Active
stack pointer bit to 1, see MSR.
perform an exception return to Thread mode with the appropriate EXC_RETURN value, see Table 2.17.
When changing the stack pointer, software must use an ISB instruction
immediately after the MSR instruction. This ensures
that instructions after the ISB instruction execute
using the new stack pointer. See ISB
| Copyright © 2010 ARM. All rights reserved. | ARM DUI 0552A |
| Non-Confidential | ID121610 |
| PDF version | |
| Home > The Cortex-M3 Processor > Programmers model > Core registers |