Cortex-M3 Devices Generic User Guide
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4.3.1. Auxiliary Control Register

The ACTLR provides disable bits for the following processor functions:

By default this register is set to provide optimum performance from the Cortex-M3 processor, and does not normally require modification.

See the register summary in Table 4.12 for the ACTLR attributes. The bit assignments are:

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Table 4.13. ACTLR bit assignments

BitsNameFunction
[31:3]-Reserved
[2]DISFOLD When set to 1, disables IT folding. see About IT folding for more information.
[1]DISDEFWBUF

When set to 1, disables write buffer use during default memory map accesses. This causes all BusFaults to be precise BusFaults but decreases performance because any store to memory must complete before the processor can execute the next instruction.

Note

This bit only affects write buffers implemented in the Cortex-M3 processor.

[0]DISMCYCINT When set to 1, disables interruption of load multiple and store multiple instructions. This increases the interrupt latency of the processor because any LDM or STM must complete before the processor can stack the current state and enter the interrupt handler.

About IT folding

In some situations, the processor can start executing the first instruction in an IT block while it is still executing the IT instruction. This behavior is called IT folding, and improves performance, However, IT folding can cause jitter in looping. If a task must avoid jitter, set the DISFOLD bit to 1 before executing the task, to disable IT folding.

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