Cortex-M3 Devices Generic User Guide
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4.2.3. Interrupt Clear-enable Registers

The NVIC_ICER0-NVIC_ICER7 registers disable interrupts, and show which interrupts are enabled. See the register summary in Table 4.2 for the register attributes.

The bit assignments are:

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Table 4.5. ICER bit assignments

BitsNameFunction
[31:0]CLRENA

Interrupt clear-enable bits.

Write:

0 = no effect

1 = disable interrupt.

Read:

0 = interrupt disabled

1 = interrupt enabled.


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