| Copyright © 2010 ARM. All rights reserved. | ARM DUI 0552A |
| Non-Confidential | ID121610 |
 PDF version | |
| Home > Cortex-M3 Peripherals > Optional Memory Protection Unit > MPU Region Base Address Register |
| |||
| Home > Cortex-M3 Peripherals > Optional Memory Protection Unit > MPU Region Base Address Register | |||
The MPU_RBAR defines the base address of the MPU region selected by the MPU_RNR, and can update the value of the MPU_RNR. See the register summary in Table 4.38 for its attributes.
Write MPU_RBAR with the VALID bit set to 1 to change the current region number and update the MPU_RNR. The bit assignments are:
Table 4.42. MPU_RBAR bit assignments
| Bits | Name | Function |
|---|---|---|
| [31:N] | ADDR | Region base address field. The value of N depends on the region size. For more information see The ADDR field. |
| [(N-1):5] | - | Reserved. |
| [4] | VALID | MPU Region Number valid bit: Write: 0 = MPU_RNR not changed, and the processor:
1 = the processor:
Always reads as zero. |
| [3:0] | REGION | MPU region field: For the behavior on writes, see the description of the VALID field. On reads, returns the current region number, as specified by the RNR. |
The ADDR field is bits[31:N] of the MPU_RBAR. The region size, as specified by the SIZE field in the MPU_RASR, defines the value of N:
N = Log2(Region size in bytes),
If the region size is configured to 4GB, in the MPU_RASR,
there is no valid ADDR field. In this case, the region occupies
the complete memory map, and the base address is 0x00000000.
The base address is aligned to the size of the region. For
example, a 64KB region must be aligned on a multiple of 64KB, for
example, at 0x00010000 or 0x00020000.
| Copyright © 2010 ARM. All rights reserved. | ARM DUI 0552A |
| Non-Confidential | ID121610 |
| PDF version | |
| Home > Cortex-M3 Peripherals > Optional Memory Protection Unit > MPU Region Base Address Register |