Cortex-M4 Devices Generic User Guide: 4.6. Floating Point Unit (FPU)

4.6. Floating Point Unit (FPU)

This section describes the optional Floating Point Unit (FPU) in a Cortex-M4F device. The FPU implements the FPv4-SP floating-point extension.

The FPU fully supports single-precision add, subtract, multiply, divide, multiply and accumulate, and square root operations. It also provides conversions between fixed-point and floating-point data formats, and floating-point constant instructions.

The FPU provides floating-point computation functionality that is compliant with the ANSI/IEEE Std 754-2008, IEEE Standard for Binary Floating-Point Arithmetic, referred to as the IEEE 754 standard.

The FPU contains 32 single-precision extension registers, which you can also access as 16 doubleword registers for load, store, and move operations.

Table 4.49 shows the floating-point system registers in the Cortex-M4F FPU.

Table 4.49. Cortex-M4F floating-point system registers

Address	Name	Type	Reset	Description
`0xE000ED88`	CPACR	RW	`0x00000000`	Coprocessor Access Control Register
`0xE000EF34`	FPCCR	RW	`0xC0000000`	Floating-point Context Control Register
`0xE000EF38`	FPCAR	RW	-	Floating-point Context Address Register
-	FPSCR	RW	-	Floating-point Status Control Register
`0xE000EF3C`	FPDSCR	RW	`0x00000000`	Floating-point Default Status Control Register

The following sections describe the floating-point system registers whose implementation is specific to this processor.

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