Cortex-M4 Devices Generic User Guide: 3.1. Instruction set summary

3.1. Instruction set summary

The processor implements a version of the Thumb instruction set. Table 3.1 lists the supported instructions.

Note

angle brackets, <>, enclose alternative forms of the operand
braces, {}, enclose optional operands
the Operands column is not exhaustive
Op2 is a flexible second operand that can be either a register or a constant
most instructions can use an optional condition code suffix.

For more information on the instructions and operands, see the instruction descriptions.

Table 3.1. Cortex-M4 instructions

Mnemonic	Operands	Brief description	Flags	Page
`ADC, ADCS`	`{Rd,}` `Rn,` `Op2`	Add with Carry	N,Z,C,V	ADD, ADC, SUB, SBC, and RSB
`ADD, ADDS`	`{Rd,}` `Rn,` `Op2`	Add	N,Z,C,V	ADD, ADC, SUB, SBC, and RSB
`ADD, ADDW`	`{Rd,}` `Rn,` `#imm12`	Add	-	ADD, ADC, SUB, SBC, and RSB
`ADR`	`Rd,` `label`	Load PC-relative Address	-	ADR
`AND, ANDS`	`{Rd,}` `Rn,` `Op2`	Logical AND	N,Z,C	AND, ORR, EOR, BIC, and ORN
`ASR, ASRS`	`Rd,` `Rm,` `<Rs\|#n>`	Arithmetic Shift Right	N,Z,C	ASR, LSL, LSR, ROR, and RRX
`B`	`label`	Branch	-	B, BL, BX, and BLX
`BFC`	`Rd,` `#lsb,` `#width`	Bit Field Clear	-	BFC and BFI
`BFI`	`Rd,` `Rn,` `#lsb,` `#width`	Bit Field Insert	-	BFC and BFI
`BIC, BICS`	`{Rd,}` `Rn,` `Op2`	Bit Clear	N,Z,C	AND, ORR, EOR, BIC, and ORN
`BKPT`	`#imm`	Breakpoint	-	BKPT
`BL`	`label`	Branch with Link	-	B, BL, BX, and BLX
`BLX`	`Rm`	Branch indirect with Link	-	B, BL, BX, and BLX
`BX`	`Rm`	Branch indirect	-	B, BL, BX, and BLX
`CBNZ`	`Rn,` `label`	Compare and Branch if Non Zero	-	CBZ and CBNZ
`CBZ`	`Rn,` `label`	Compare and Branch if Zero	-	CBZ and CBNZ
`CLREX`	-	Clear Exclusive	-	CLREX
`CLZ`	`Rd,` `Rm`	Count Leading Zeros	-	CLZ
`CMN`	`Rn,` `Op2`	Compare Negative	N,Z,C,V	CMP and CMN
`CMP`	`Rn,` `Op2`	Compare	N,Z,C,V	CMP and CMN
`CPSID`	`i`	Change Processor State, Disable Interrupts	-	CPS
`CPSIE`	`i`	Change Processor State, Enable Interrupts	-	CPS
`DMB`	`-`	Data Memory Barrier	-	DMB
`DSB`	`-`	Data Synchronization Barrier	-	DSB
`EOR, EORS`	`{Rd,}` `Rn,` `Op2`	Exclusive OR	N,Z,C	AND, ORR, EOR, BIC, and ORN
`ISB`	`-`	Instruction Synchronization Barrier	-	ISB
`IT`	-	If-Then condition block	-	IT
`LDM`	`Rn{!},` `reglist`	Load Multiple registers, increment after	-	LDM and STM
`LDMDB, LDMEA`	`Rn{!},` `reglist`	Load Multiple registers, decrement before	-	LDM and STM
`LDMFD, LDMIA`	`Rn{!},` `reglist`	Load Multiple registers, increment after	-	LDM and STM
`LDR`	`Rt, [Rn,` `#offset]`	Load Register with word	-	Memory access instructions
`LDRB, LDRBT`	`Rt, [Rn,` `#offset]`	Load Register with byte	-	Memory access instructions
`LDRD`	`Rt,` `Rt2, [Rn,` `#offset]`	Load Register with two bytes	-	LDR and STR, immediate offset
`LDREX`	`Rt, [Rn,` `#offset]`	Load Register Exclusive	-	LDREX and STREX
`LDREXB`	`Rt, [Rn]`	Load Register Exclusive with Byte	-	LDREX and STREX
`LDREXH`	`Rt,` `[Rn]`	Load Register Exclusive with Halfword	-	LDREX and STREX
`LDRH, LDRHT`	`Rt, [Rn,` `#offset]`	Load Register with Halfword	-	Memory access instructions
`LDRSB, LDRSBT`	`Rt, [Rn,` `#offset]`	Load Register with Signed Byte	-	Memory access instructions
`LDRSH, LDRSHT`	`Rt, [Rn,` `#offset]`	Load Register with Signed Halfword	-	Memory access instructions
`LDRT`	`Rt, [Rn,` `#offset]`	Load Register with word	-	Memory access instructions
`LSL, LSLS`	`Rd,` `Rm,` `<Rs\|#n>`	Logical Shift Left	N,Z,C	ASR, LSL, LSR, ROR, and RRX
`LSR, LSRS`	`Rd,` `Rm,` `<Rs\|#n>`	Logical Shift Right	N,Z,C	ASR, LSL, LSR, ROR, and RRX
`MLA`	`Rd,` `Rn,` `Rm, Ra`	Multiply with Accumulate, 32-bit result	-	MUL, MLA, and MLS
`MLS`	`Rd,` `Rn,` `Rm, Ra`	Multiply and Subtract, 32-bit result	-	MUL, MLA, and MLS
`MOV, MOVS`	`Rd,` `Op2`	Move	N,Z,C	MOV and MVN
`MOVT`	`Rd,` `#imm16`	Move Top	-	MOVT
`MOVW, MOV`	`Rd,` `#imm16`	Move 16-bit constant	N,Z,C	MOV and MVN
`MRS`	`Rd,` `spec_reg`	Move from Special Register to general register	-	MRS
`MSR`	`spec_reg,` `Rm`	Move from general register to Special Register	N,Z,C,V	MSR
`MUL, MULS`	`{Rd,}` `Rn,` `Rm`	Multiply, 32-bit result	N,Z	MUL, MLA, and MLS
`MVN, MVNS`	`Rd,` `Op2`	Move NOT	N,Z,C	MOV and MVN
`NOP`	-	No Operation	-	NOP
`ORN, ORNS`	`{Rd,}` `Rn,` `Op2`	Logical OR NOT	N,Z,C	AND, ORR, EOR, BIC, and ORN
`ORR, ORRS`	`{Rd,}` `Rn,` `Op2`	Logical OR	N,Z,C	AND, ORR, EOR, BIC, and ORN
`PKHTB`, `PKHBT`	`{Rd,}` `Rn,` `Rm,` `Op2`	Pack Halfword	-	PKHBT and PKHTB
`POP`	`reglist`	Pop registers from stack	-	PUSH and POP
`PUSH`	`reglist`	Push registers onto stack	-	PUSH and POP
`QADD`	`{Rd,}` `Rn,` `Rm`	Saturating double and Add	Q	QADD and QSUB
`QADD16`	`{Rd,}` `Rn,` `Rm`	Saturating Add 16	-	QADD and QSUB
`QADD8`	`{Rd,}` `Rn,` `Rm`	Saturating Add 8	-	QADD and QSUB
`QASX`	`{Rd,}` `Rn,` `Rm`	Saturating Add and Subtract with Exchange	-	QASX and QSAX
`QDADD`	`{Rd,}` `Rn,` `Rm`	Saturating Add	Q	QDADD and QDSUB
`QDSUB`	`{Rd,}` `Rn,` `Rm`	Saturating double and Subtract	Q	QDADD and QDSUB
`QSAX`	`{Rd,}` `Rn,` `Rm`	Saturating Subtract and Add with Exchange	-	QASX and QSAX
`QSUB`	`{Rd,}` `Rn,` `Rm`	Saturating Subtract	Q	QDADD and QDSUB
`QSUB16`	`{Rd,}` `Rn,` `Rm`	Saturating Subtract 16	-	QDADD and QDSUB
`QSUB8`	`{Rd,}` `Rn,` `Rm`	Saturating Subtract 8	-	QDADD and QDSUB
`RBIT`	`Rd,` `Rn`	Reverse Bits	-	REV, REV16, REVSH, and RBIT
`REV`	`Rd,` `Rn`	Reverse byte order in a word	-	REV, REV16, REVSH, and RBIT
`REV16`	`Rd,` `Rn`	Reverse byte order in each halfword	-	REV, REV16, REVSH, and RBIT
`REVSH`	`Rd,` `Rn`	Reverse byte order in bottom halfword and sign extend	-	REV, REV16, REVSH, and RBIT
`ROR, RORS`	`Rd,` `Rm,` `<Rs\|#n>`	Rotate Right	N,Z,C	ASR, LSL, LSR, ROR, and RRX
`RRX, RRXS`	`Rd,` `Rm`	Rotate Right with Extend	N,Z,C	ASR, LSL, LSR, ROR, and RRX
`RSB, RSBS`	`{Rd,}` `Rn,` `Op2`	Reverse Subtract	N,Z,C,V	ADD, ADC, SUB, SBC, and RSB
`SADD16`	`{Rd,}` `Rn,` `Rm`	Signed Add 16	GE	SADD16 and SADD8
`SADD8`	`{Rd,}` `Rn,` `Rm`	Signed Add 8	GE	SADD16 and SADD8
`SASX`	`{Rd,}` `Rn,` `Rm`	Signed Add and Subtract with Exchange	GE	SASX and SSAX
`SBC, SBCS`	`{Rd,}` `Rn,` `Op2`	Subtract with Carry	N,Z,C,V	ADD, ADC, SUB, SBC, and RSB
`SBFX`	`Rd,` `Rn,` `#lsb,` `#width`	Signed Bit Field Extract	-	SBFX and UBFX
`SDIV`	`{Rd,}` `Rn,` `Rm`	Signed Divide	-	SDIV and UDIV
`SEL`	`{Rd,}` `Rn,` `Rm`	Select bytes	-	SEL
`SEV`	-	Send Event	-	SEV
`SHADD16`	`{Rd,}` `Rn,` `Rm`	Signed Halving Add 16	-	SHADD16 and SHADD8
`SHADD8`	`{Rd,}` `Rn,` `Rm`	Signed Halving Add 8	-	SHADD16 and SHADD8
`SHASX`	`{Rd,}` `Rn,` `Rm`	Signed Halving Add and Subtract with Exchange	-	SHASX and SHSAX
`SHSAX`	`{Rd,}` `Rn,` `Rm`	Signed Halving Subtract and Add with Exchange	-	SHASX and SHSAX
`SHSUB16`	`{Rd,}` `Rn,` `Rm`	Signed Halving Subtract 16	-	SHSUB16 and SHSUB8
`SHSUB8`	`{Rd,}` `Rn,` `Rm`	Signed Halving Subtract 8	-	SHSUB16 and SHSUB8
`SMLABB, SMLABT, SMLATB, SMLATT`	`Rd,` `Rn,` `Rm, Ra`	Signed Multiply Accumulate Long (halfwords)	Q	SMLA and SMLAW
`SMLAD`, `SMLADX`	`Rd,` `Rn,` `Rm, Ra`	Signed Multiply Accumulate Dual	Q	SMLAD
`SMLAL`	`RdLo, RdHi, Rn, Rm`	Signed Multiply with Accumulate (32 x 32 + 64), 64-bit result	-	UMULL, UMLAL, SMULL, and SMLAL
`SMLALBB, SMLALBT, SMLALTB, SMLALTT`	`RdLo, RdHi, Rn, Rm`	Signed Multiply Accumulate Long, halfwords	-	SMLAL and SMLALD
`SMLALD`, `SMLALDX`	`RdLo, RdHi, Rn, Rm`	Signed Multiply Accumulate Long Dual	-	SMLAL and SMLALD
`SMLAWB, SMLAWT`	`Rd,` `Rn,` `Rm, Ra`	Signed Multiply Accumulate, word by halfword	Q	SMLA and SMLAW
`SMLSD`	`Rd,` `Rn,` `Rm, Ra`	Signed Multiply Subtract Dual	Q	SMLSD and SMLSLD
`SMLSLD`	`RdLo, RdHi, Rn, Rm`	Signed Multiply Subtract Long Dual		SMLSD and SMLSLD
`SMMLA`	`Rd,` `Rn,` `Rm, Ra`	Signed Most significant word Multiply Accumulate	-	SMMLA and SMMLS
`SMMLS`, `SMMLR`	`Rd,` `Rn,` `Rm, Ra`	Signed Most significant word Multiply Subtract	-	SMMLA and SMMLS
`SMMUL, SMMULR`	`{Rd,}` `Rn,` `Rm`	Signed Most significant word Multiply	-	SMMUL
`SMUAD`	`{Rd,}` `Rn,` `Rm`	Signed dual Multiply Add	Q	SMUAD and SMUSD
`SMULBB, SMULBT SMULTB, SMULTT`	`{Rd,}` `Rn,` `Rm`	Signed Multiply (halfwords)	-	SMUL and SMULW
`SMULL`	`RdLo, RdHi, Rn, Rm`	Signed Multiply (32 x 32), 64-bit result	-	UMULL, UMLAL, SMULL, and SMLAL
`SMULWB,` `SMULWT`	`{Rd,}` `Rn,` `Rm`	Signed Multiply word by halfword	-	SMUL and SMULW
`SMUSD`, `SMUSDX`	`{Rd,}` `Rn,` `Rm`	Signed dual Multiply Subtract	-	SMUAD and SMUSD
`SSAT`	`Rd, #n, Rm {,shift #s}`	Signed Saturate	Q	SSAT and USAT
`SSAT16`	`Rd, #n, Rm`	Signed Saturate 16	Q	SSAT16 and USAT16
`SSAX`	`{Rd,}` `Rn,` `Rm`	Signed Subtract and Add with Exchange	GE	SASX and SSAX
`SSUB16`	`{Rd,}` `Rn,` `Rm`	Signed Subtract 16	-	SSUB16 and SSUB8
`SSUB8`	`{Rd,}` `Rn,` `Rm`	Signed Subtract 8	-	SSUB16 and SSUB8
`STM`	`Rn{!},` `reglist`	Store Multiple registers, increment after	-	LDM and STM
`STMDB, STMEA`	`Rn{!},` `reglist`	Store Multiple registers, decrement before	-	LDM and STM
`STMFD, STMIA`	`Rn{!},` `reglist`	Store Multiple registers, increment after	-	LDM and STM
`STR`	`Rt, [Rn,` `#offset]`	Store Register word	-	Memory access instructions
`STRB, STRBT`	`Rt, [Rn,` `#offset]`	Store Register byte	-	Memory access instructions
`STRD`	`Rt,` `Rt2, [Rn,` `#offset]`	Store Register two words	-	LDR and STR, immediate offset
`STREX`	`Rd,` `Rt, [Rn,` `#offset]`	Store Register Exclusive	-	LDREX and STREX
`STREXB`	`Rd,` `Rt,` `[Rn]`	Store Register Exclusive Byte	-	LDREX and STREX
`STREXH`	`Rd,` `Rt,` `[Rn]`	Store Register Exclusive Halfword	-	LDREX and STREX
`STRH, STRHT`	`Rt, [Rn,` `#offset]`	Store Register Halfword	-	Memory access instructions
`STRT`	`Rt, [Rn,` `#offset]`	Store Register word	-	Memory access instructions
`SUB, SUBS`	`{Rd,}` `Rn,` `Op2`	Subtract	N,Z,C,V	ADD, ADC, SUB, SBC, and RSB
`SUB, SUBW`	`{Rd,}` `Rn,` `#imm12`	Subtract	-	ADD, ADC, SUB, SBC, and RSB
`SVC`	`#imm`	Supervisor Call	-	SVC
`SXTAB`	`{Rd,} Rn, Rm,{,ROR #}`	Extend 8 bits to 32 and add	-	SXTA and UXTA
`SXTAB16`	`{Rd,} Rn, Rm,{,ROR #}`	Dual extend 8 bits to 16 and add	-	SXTA and UXTA
`SXTAH`	`{Rd,} Rn, Rm,{,ROR #}`	Extend 16 bits to 32 and add	-	SXTA and UXTA
`SXTB16`	`{Rd,} Rm {,ROR #n}`	Signed Extend Byte 16	-	SXT and UXT
`SXTB`	`{Rd,} Rm {,ROR #n}`	Sign extend a byte	-	SXT and UXT
`SXTH`	`{Rd,} Rm {,ROR #n}`	Sign extend a halfword	-	SXT and UXT
`TBB`	`[Rn, Rm]`	Table Branch Byte	-	TBB and TBH
`TBH`	`[Rn, Rm, LSL #1]`	Table Branch Halfword	-	TBB and TBH
`TEQ`	`Rn, Op2`	Test Equivalence	N,Z,C	TST and TEQ
`TST`	`Rn, Op2`	Test	N,Z,C	TST and TEQ
`UADD16`	`{Rd,}` `Rn,` `Rm`	Unsigned Add 16	GE	UADD16 and UADD8
`UADD8`	`{Rd,}` `Rn,` `Rm`	Unsigned Add 8	GE	UADD16 and UADD8
`USAX`	`{Rd,}` `Rn,` `Rm`	Unsigned Subtract and Add with Exchange	GE	UASX and USAX
`UHADD16`	`{Rd,}` `Rn,` `Rm`	Unsigned Halving Add 16	-	UHADD16 and UHADD8
`UHADD8`	`{Rd,}` `Rn,` `Rm`	Unsigned Halving Add 8	-	UHADD16 and UHADD8
`UHASX`	`{Rd,}` `Rn,` `Rm`	Unsigned Halving Add and Subtract with Exchange	-	UHASX and UHSAX
`UHSAX`	`{Rd,}` `Rn,` `Rm`	Unsigned Halving Subtract and Add with Exchange	-	UHASX and UHSAX
`UHSUB16`	`{Rd,}` `Rn,` `Rm`	Unsigned Halving Subtract 16	-	UHSUB16 and UHSUB8
`UHSUB8`	`{Rd,}` `Rn,` `Rm`	Unsigned Halving Subtract 8	-	UHSUB16 and UHSUB8
`UBFX`	`Rd,` `Rn,` `#lsb,` `#width`	Unsigned Bit Field Extract	-	SBFX and UBFX
`UDIV`	`{Rd,}` `Rn,` `Rm`	Unsigned Divide	-	SDIV and UDIV
`UMAAL`	`RdLo, RdHi, Rn, Rm`	Unsigned Multiply Accumulate Accumulate Long (32 x 32 + 32 +32), 64-bit result	-	UMULL, UMAAL, UMLAL
`UMLAL`	`RdLo, RdHi, Rn, Rm`	Unsigned Multiply with Accumulate (32 x 32 + 64), 64-bit result	-	UMULL, UMLAL, SMULL, and SMLAL
`UMULL`	`RdLo, RdHi, Rn, Rm`	Unsigned Multiply (32 x 32), 64-bit result	-	UMULL, UMLAL, SMULL, and SMLAL
`UQADD16`	`{Rd,}` `Rn,` `Rm`	Unsigned Saturating Add 16	-	UQADD and UQSUB
`UQADD8`	`{Rd,}` `Rn,` `Rm`	Unsigned Saturating Add 8	-	UQADD and UQSUB
`UQASX`	`{Rd,}` `Rn,` `Rm`	Unsigned Saturating Add and Subtract with Exchange	-	UQASX and UQSAX
`UQSAX`	`{Rd,}` `Rn,` `Rm`	Unsigned Saturating Subtract and Add with Exchange	-	UQASX and UQSAX
`UQSUB16`	`{Rd,}` `Rn,` `Rm`	Unsigned Saturating Subtract 16	-	UQADD and UQSUB
`UQSUB8`	`{Rd,}` `Rn,` `Rm`	Unsigned Saturating Subtract 8	-	UQADD and UQSUB
`USAD8`	`{Rd,}` `Rn,` `Rm`	Unsigned Sum of Absolute Differences	-	USAD8
`USADA8`	`{Rd,}` `Rn,` `Rm, Ra`	Unsigned Sum of Absolute Differences and Accumulate	-	USADA8
`USAT`	`Rd, #n, Rm {,shift #s}`	Unsigned Saturate	Q	SSAT and USAT
`USAT16`	Rd, #n, Rm	Unsigned Saturate 16	Q	SSAT16 and USAT16
`UASX`	`{Rd,}` `Rn,` `Rm`	Unsigned Add and Subtract with Exchange	GE	UASX and USAX
`USUB16`	`{Rd,}` `Rn,` `Rm`	Unsigned Subtract 16	GE	USUB16 and USUB8
`USUB8`	`{Rd,}` `Rn,` `Rm`	Unsigned Subtract 8	GE	USUB16 and USUB8
`UXTAB`	`{Rd,} Rn, Rm,{,ROR #}`	Rotate, extend 8 bits to 32 and Add	-	SXTA and UXTA
`UXTAB16`	`{Rd,} Rn, Rm,{,ROR #}`	Rotate, dual extend 8 bits to 16 and Add	-	SXTA and UXTA
`UXTAH`	`{Rd,} Rn, Rm,{,ROR #}`	Rotate, unsigned extend and Add Halfword	-	SXTA and UXTA
`UXTB`	`{Rd,} Rm {,ROR #n}`	Zero extend a Byte	-	SXT and UXT
`UXTB16`	`{Rd,} Rm {,ROR #n}`	Unsigned Extend Byte 16	-	SXT and UXT
`UXTH`	`{Rd,} Rm {,ROR #n}`	Zero extend a Halfword	-	SXT and UXT
`VABS.F32`	`Sd, Sm`	Floating-point Absolute	-	VABS
`VADD.F32`	`{Sd,} Sn, Sm`	Floating-point Add	-	VADD
`VCMP.F32`	`Sd, <Sm \| #0.0>`	Compare two floating-point registers, or one floating-point register and zero	FPSCR	VCMP, VCMPE
`VCMPE.F32`	`Sd, <Sm \| #0.0>`	Compare two floating-point registers, or one floating-point register and zero with Invalid Operation check	FPSCR	VCMP, VCMPE
`VCVT.S32.F32`	`Sd, Sm`	Convert between floating-point and integer	-	VCVT, VCVTR between floating-point and integer
`VCVT.S16.F32`	`Sd, Sd, #fbits`	Convert between floating-point and fixed point	-	VCVT between floating-point and fixed-point
`VCVTR.S32.F32`	`Sd, Sm`	Convert between floating-point and integer with rounding	-	VCVT, VCVTR between floating-point and integer
`VCVT<B\|H>.F32.F16`	`Sd, Sm`	Converts half-precision value to single-precision	-	VCVTB, VCVTT
`VCVTT<B\|T>.F32.F16`	`Sd, Sm`	Converts single-precision register to half-precision	-	VCVTB, VCVTT
`VDIV.F32`	`{Sd,} Sn, Sm`	Floating-point Divide	-	VDIV
`VFMA.F32`	`{Sd,} Sn, Sm`	Floating-point Fused Multiply Accumulate	-	VFMA, VFMS
`VFNMA.F32`	`{Sd,} Sn, Sm`	Floating-point Fused Negate Multiply Accumulate	-	VFNMA, VFNMS
`VFMS.F32`	`{Sd,} Sn, Sm`	Floating-point Fused Multiply Subtract	-	VFMA, VFMS
`VFNMS.F32`	`{Sd,} Sn, Sm`	Floating-point Fused Negate Multiply Subtract	-	VFNMA, VFNMS
`VLDM.F<32\|64>`	`Rn{!}, list`	Load Multiple extension registers	-	VLDM
`VLDR.F<32\|64>`	<`Dd\|Sd>, [Rn]`	Load an extension register from memory	-	VLDR
`VLMA.F32`	`{Sd,} Sn, Sm`	Floating-point Multiply Accumulate	-	VLMA, VLMS
`VLMS.F32`	`{Sd,} Sn, Sm`	Floating-point Multiply Subtract	-	VLMA, VLMS
`VMOV.F32`	`Sd, #imm`	Floating-point Move immediate	-	VMOV Immediate
`VMOV`	`Sd, Sm`	Floating-point Move register	-	VMOV Register
`VMOV`	`Sn, Rt`	Copy ARM core register to single precision	-	VMOV ARM Core register to single precision
`VMOV`	`Sm, Sm1, Rt, Rt2`	Copy 2 ARM core registers to 2 single precision	-	VMOV Two ARM Core registers to two single precision
`VMOV`	`Dd[x], Rt`	Copy ARM core register to scalar	-	VMOV ARM Core register to scalar
`VMOV`	`Rt, Dn[x]`	Copy scalar to ARM core register	-	VMOV Scalar to ARM Core register
`VMRS`	`Rt, FPSCR`	Move FPSCR to ARM core register or APSR	N,Z,C,V	VMRS
`VMSR`	`FPSCR, Rt`	Move to FPSCR from ARM Core register	FPSCR	VMSR
`VMUL.F32`	`{Sd,} Sn, Sm`	Floating-point Multiply	-	VMUL
`VNEG.F32`	`Sd, Sm`	Floating-point Negate	-	VNEG
`VNMLA.F32`	`Sd, Sn, Sm`	Floating-point Multiply and Add	-	VNMLA, VNMLS, VNMUL
`VNMLS.F32`	`Sd, Sn, Sm`	Floating-point Multiply and Subtract	-	VNMLA, VNMLS, VNMUL
`VNMUL`	`{Sd,} Sn, Sm`	Floating-point Multiply	-	VNMLA, VNMLS, VNMUL
`VPOP`	`list`	Pop extension registers	-	VPOP
`VPUSH`	`list`	Push extension registers	-	VPUSH
`VSQRT.F32`	`Sd, Sm`	Calculates floating-point Square Root	-	VSQRT
`VSTM`	`Rn{!}, list`	Floating-point register Store Multiple	-	VSTM
`VSTR.F<32\|64>`	`Sd, [Rn]`	Stores an extension register to memory	-	VSTR
`VSUB.F<32\|64>`	`{Sd,} Sn, Sm`	Floating-point Subtract	-	VSUB
`WFE`	-	Wait For Event	-	WFE
`WFI`	-	Wait For Interrupt	-	WFI

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