### 3.6.5. SMLAL and SMLALD

Signed Multiply Accumulate Long, Signed Multiply Accumulate Long (halfwords) and Signed Multiply Accumulate Long Dual.

#### Syntax

````op`{`cond`} `RdLo`, `RdHi`, `Rn`, `Rm`
```
````op`{XY}{`cond`} `RdLo`, `RdHi`, `Rn`, `Rm`
```
````op`{`X`}{`cond`} `RdLo`, `RdHi`, `Rn`, `Rm`
```

where:

`op`

Is one of:

, `SMLAL`

Signed Multiply Accumulate Long

`SMLAL`

Signed Multiply Accumulate Long (halfwords, X and Y)

X and Y specify which halfword of the source registers `Rn` and `Rm` are used as the first and second multiply operand:

If `X` is `B`, then the bottom halfword, bits [15:0], of `Rn` is used. If `X` is `T`, then the top halfword, bits [31:16], of `Rn` is used.

If `Y` is `B`, then the bottom halfword, bits [15:0], of `Rm` is used. If `Y` is `T`, then the top halfword, bits [31:16], of `Rm` is used.

`SMLALD`

Signed Multiply Accumulate Long Dual

`SMLALDX`

Signed Multiply Accumulate Long Dual Reversed

If the `X` is omitted, the multiplications are bottom × bottom and top × top.

If `X` is present, the multiplications are bottom × top and top × bottom.

`cond`

Is an optional condition code, see Conditional execution.

`RdHi, RdLo`

Are the destination registers. `RdLo` is the lower 32 bits and `RdHi` is the upper 32 bits of the 64-bit integer. For `SMLAL`, `SMLALBB`, `SMLALBT`, `SMLALTB`, `SMLALTT`, `SMLALD` and `SMLALDX,` they also hold the accumulating value.

`Rn, Rm`

Are registers holding the first and second operands.

#### Operation

The `SMLAL` instruction:

• Multiplies the two’s complement signed word values from `Rn` and `Rm`.

• Adds the 64-bit value in `RdLo` and `RdHi` to the resulting 64-bit product.

• Writes the 64-bit result of the multiplication and addition in `RdLo`` and ``RdHi`.

The `SMLALBB`, `SMLALBT`, `SMLALTB` and `SMLALTT` instructions:

• Multiplies the specified signed halfword, Top or Bottom, values from `Rn` and `Rm`.

• Adds the resulting sign-extended 32-bit product to the 64-bit value in `RdLo `and `RdHi`.

• Writes the 64-bit result of the multiplication and addition in `RdLo `and `RdHi`.

The non-specified halfwords of the source registers are ignored.

The `SMLALD` and `SMLALDX` instructions interpret the values from `Rn` and `Rm` as four halfword two’s complement signed 16-bit integers. These instructions:

• if `X` is not present, multiply the top signed halfword value of `Rn` with the top signed halfword of `Rm` and the bottom signed halfword values of `Rn` with the bottom signed halfword of `Rm`.

• Or if `X` is present, multiply the top signed halfword value of `Rn` with the bottom signed halfword of `Rm` and the bottom signed halfword values of `Rn` with the top signed halfword of `Rm`.

• Add the two multiplication results to the signed 64-bit value in `RdLo` and `RdHi` to create the resulting 64-bit product.

• Write the 64-bit product in `RdLo` and `RdHi`.

#### Restrictions

In these instructions:

• do not use SP and do not use PC.

• `RdHi` and `RdLo` must be different registers.

#### Condition flags

These instructions do not affect the condition code flags.

#### Examples

```SMLAL       R4, R5, R3, R8   ; Multiplies R3 and R8, adds R5:R4 and writes to
```
```                             ; R5:R4
```
```SMLALBT     R2, R1, R6, R7   ; Multiplies bottom halfword of R6 with top
```
```                             ; halfword of R7, sign extends to 32-bit, adds
```
```                             ; R1:R2 and writes to R1:R2
```
```SMLALTB     R2, R1, R6, R7   ; Multiplies top halfword of R6 with bottom
```
```                             ; halfword of R7, sign extends to 32-bit, adds R1:R2
```
```                             ; and writes to R1:R2
```
```SMLALD      R6, R8, R5, R1   ; Multiplies top halfwords in R5 and R1 and bottom
```
```                             ; halfwords of R5 and R1, adds R8:R6 and writes to
```
```                             ; R8:R6
```
```SMLALDX     R6, R8, R5, R1   ; Multiplies top halfword in R5 with bottom
```
```                             ; halfword of R1, and bottom halfword of R5 with
; top halfword of R1, adds R8:R6 and writes to
```
```                             ; R8:R6.
```
```
```