Cortex-M4 Devices Generic User Guide: 4.1. About the Cortex-M4 peripherals

Cortex-M4 Devices Generic User Guide

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4.1. About the Cortex-M4 peripherals

The address map of the Private Peripheral Bus (PPB) is:

Table 4.1. Core peripheral register regions

Address	Core peripheral	Description
`0xE000E008`-`0xE000E00F`	SyStem Control Block	Table 4.12
`0xE000E010`-`0xE000E01F`	System timer	Table 4.32
`0xE000E100`-`0xE000E4EF`	Nested Vectored Interrupt Controller	Table 4.2
`0xE000ED00`-`0xE000ED3F`	System Control Block	Table 4.12
`0xE000ED90`-`0xE000ED93`	MPU Type Register	Reads as zero, indicating MPU is not implemented ^[a]
`0xE000ED90`-`0xE000EDB8`	Memory Protection Unit	Table 4.38
`0xE000EF00`-`0xE000EF03`	Nested Vectored Interrupt Controller	Table 4.2
`0xE000EF30`-`0xE000EF44`	Floating Point Unit	Table 4.49
^[a]Software can read the MPU Type Register at `0xE000ED90` to test for the presence of a Memory Protection Unit (MPU)

In register descriptions:

the register type is described as follows:
RW
Read and write.
RO
Read-only.
WO
Write-only.
the required privilege gives the privilege level required to access the register, as follows:
Privileged
Only privileged software can access the register.
Unprivileged
Both unprivileged and privileged software can access the register.

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