Cortex-M4 Devices Generic User Guide
Home > Cortex-M4 Peripherals > Nested Vectored Interrupt Controller > Interrupt Clear-pending Registers

4.2.5. Interrupt Clear-pending Registers

The NVIC_ICPR0-NCVIC_ICPR7 registers remove the pending state from interrupts, and show which interrupts are pending. See the register summary in Table 4.2 for the register attributes.

The bit assignments are:

To view this graphic, your browser must support the SVG format. Either install a browser with native support, or install an appropriate plugin such as Adobe SVG Viewer.

Table 4.7. ICPR bit assignments

BitsNameFunction
[31:0]CLRPEND

Interrupt clear-pending bits.

Write:

0 = no effect

1 = removes pending state an interrupt.

Read:

0 = interrupt is not pending

1 = interrupt is pending.


Note

Writing 1 to an ICPR bit does not affect the active state of the corresponding interrupt.

Copyright © 2010 ARM. All rights reserved.ARM DUI 0553A
Non-ConfidentialID121610
PDF file icon  PDF version
Home > Cortex-M4 Peripherals > Nested Vectored Interrupt Controller > Interrupt Clear-pending Registers