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The MPU_RASR defines the region size and memory attributes of the MPU region specified by the MPU_RNR, and enables that region and any subregions. See the register summary in Table 4.38 for its attributes.
MPU_RASR is accessible using word or halfword accesses:
the most significant halfword holds the region attributes
the least significant halfword holds the region size and the region and subregion enable bits.
The bit assignments are:
Table 4.43. MPU_RASR bit assignments
| Bits | Name | Function |
|---|---|---|
| [31:29] | - | Reserved. |
| [28] | XN | Instruction access disable bit: 0 = instruction fetches enabled 1 = instruction fetches disabled. |
| [27] | - | Reserved. |
| [26:24] | AP | Access permission field, see Table 4.47. |
| [23:22] | - | Reserved. |
| [21:19, 17, 16] | TEX, C, B | Memory access attributes, see Table 4.45. |
| [18] | S | Shareable bit, see Table 4.45. |
| [15:8] | SRD | Subregion disable bits. For each bit in this field: 0 = corresponding sub-region is enabled 1 = corresponding sub-region is disabled See Subregions for more information. Region
sizes of 128 bytes and less do not support subregions. When writing
the attributes for such a region, write the SRD field as |
| [7:6] | - | Reserved. |
| [5:1] | SIZE | Specifies the size of the MPU protection region.
The minimum permitted value is 3 (0b00010). See SIZE field values for more information. |
| [0] | ENABLE | Region enable bit. |
For information about access permission, see MPU access permission attributes.
The SIZE field defines the size of the MPU memory region specified by the RNR. as follows:
(Region size in bytes) = 2(SIZE+1)
The smallest permitted region size is 32B, corresponding to a SIZE value of 4. Table 4.44 gives example SIZE values, with the corresponding region size and value of N in the MPU_RBAR.
Table 4.44. Example SIZE field values
| SIZE value | Region size | Value of N [a] | Note |
|---|---|---|---|
0b00100 (4) | 32B | 5 | Minimum permitted size |
0b01001 (9) | 1KB | 10 | - |
0b10011 (19) | 1MB | 20 | - |
0b11101 (29) | 1GB | 30 | - |
0b11111 (31) | 4GB | 32 | Maximum possible size |
[a] In the MPU_RBAR, see MPU Region Base Address Register. | |||
| Copyright © 2010 ARM. All rights reserved. | ARM DUI 0553A |
| Non-Confidential | ID121610 |
| PDF version | |
| Home > Cortex-M4 Peripherals > Optional Memory Protection Unit > MPU Region Attribute and Size Register |