Cortex-M4 Devices Generic User Guide: 4.3.5. Application Interrupt and Reset Control Register

4.3.5. Application Interrupt and Reset Control Register

The AIRCR provides priority grouping control for the exception model, endian status for data accesses, and reset control of the system. See the register summary in Table 4.12 and Table 4.17 for its attributes.

To write to this register, you must write 0x5FA to the VECTKEY field, otherwise the processor ignores the write.

The bit assignments are:

Table 4.17. AIRCR bit assignments

Bits	Name	Type	Function
[31:16]	Write: VECTKEYSTAT Read: VECTKEY	RW	Register key: Reads as `0xFA05` On writes, write `0x5FA` to VECTKEY, otherwise the write is ignored.
[15]	ENDIANNESS	RO	Data endianness bit is implementation defined: 0 = Little-endian 1 = Big-endian.
[14:11]	-	-	Reserved.
[10:8]	PRIGROUP	R/W	Interrupt priority grouping field is implementation defined. This field determines the split of group priority from subpriority, see Binary point.
[7:3]	-	-	Reserved.
[2]	SYSRESETREQ	WO	System reset request bit is implementation defined: 0 = no system reset request 1 = asserts a signal to the outer system that requests a reset. This is intended to force a large system reset of all major components except for debug. This bit reads as 0. See you vendor documentation for more information about the use of this signal in your implementation.
[1]	VECTCLRACTIVE	WO	Reserved for Debug use. This bit reads as 0. When writing to the register you must write 0 to this bit, otherwise behavior is Unpredictable.
[0]	VECTRESET	WO	Reserved for Debug use. This bit reads as 0. When writing to the register you must write 0 to this bit, otherwise behavior is Unpredictable.

Binary point

The PRIGROUP field indicates the position of the binary point that splits the PRI_n fields in the Interrupt Priority Registers into separate group priority and subpriority fields. Table 4.18 shows how the PRIGROUP value controls this split. Implementations having fewer than 8-bits of interrupt priority treat the least significant bits as zero

Table 4.18. Priority grouping

	Interrupt priority level value, PRI_N[7:0]			Number of
PRIGROUP	Binary point ^[a]	Group priority bits	Subpriority bits	Group priorities	Subpriorities
`0b000`	bxxxxxxx.y	[7:1]	[0]	128	2
`0b001`	bxxxxxx.yy	[7:2]	[1:0]	64	4
`0b010`	bxxxxx.yyy	[7:3]	[2:0]	32	8
`0b011`	bxxxx.yyyy	[7:4]	[3:0]	16	16
`0b100`	bxxx.yyyyy	[7:5]	[4:0]	8	32
`0b101`	bxx.yyyyyy	[7:6]	[5:0]	4	64
`0b110`	bx.yyyyyyy	[7]	[6:0]	2	128
`0b111`	b.yyyyyyyy	None	[7:0]	1	256
^[a]PRI_n[7:0] field showing the binary point. x denotes a group priority field bit, and y denotes a subpriority field bit.

Note

Determining preemption of an exception uses only the group priority field, see Interrupt priority grouping.

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