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2.2.9. PCI-Express Bus (PCIe)

This connects to FPGA 1. The daughterboard can implement a root complex or endpoint to connect to the PCI-Express Gen1 Card slots on the motherboard or the other daughterboard site. A maximum of eight lanes is supported downwards, to header HDRYL, and upwards, to header HDRYU, from the daughterboard. Figure 2.4 shows the PCI-Express signals to the headers. Table 2.1 and Table 2.2 show, for each header, the connectivity between the Gigabit Transceiver (GTX) locations in FPGA 1 and the PCI-Express lanes.

Note

Xilinx supplies the PCIe endpoint and the PCIe root port in the Virtex-6 FPGA as hardblocks. You can implement them using Xilinx tool flow. You can implement a PCIe root complex using a third party IP softblock.

Figure 2.4. PCI express bus connections

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Caution

You can configure the sideband signals PCIe_nWAKE, PCIe_PERST, and PCIe_nRST as either inputs or outputs. If you configure them as outputs, they must be set to be open-collector.

Note

  • When the daughterboard is fitted to the motherboard, HDRYU is on the upper side of the board facing away from the motherboard, and HDRYL is on the lower side of the board facing towards the motherboard.

  • Clocks PCIe_UP_REFCLK and PCIe_UP_LOCAL_REFCLK are synchronous.

Table 2.1 shows, for the upper header, the connectivity between the Gigabit Transceiver (GTX) locations in FPGA 1 and the PCI-Express lanes.

Table 2.1. Upper header PCI-Express Lanes. FPGA 1-GTX connectivity

PCIe laneGTX location
Lane 0X0Y15
Lane 1X0Y14
Lane 2X0Y13
Lane 3X0Y12
Lane 4X0Y11
Lane 5X0Y10
Lane 6X0Y9
Lane 7X0Y8

Table 2.2 shows, for the lower header, the connectivity between the GTX locations in FPGA 1 and the PCI-Express lanes.

Table 2.2. Lower header PCI-Express Lanes. FPGA 1-GTX connectivity

PCIe laneGTX location
Lane 0X0Y23
Lane 1X0Y22
Lane 2X0Y21
Lane 3X0Y20
Lane 4X0Y19
Lane 5X0Y18
Lane 6X0Y17
Lane 7X0Y16

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